@@ -40,8 +40,6 @@
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
-#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
-
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000
#define GICR_BASE 0x06100000
@@ -49,8 +47,6 @@
/* SMMU Defintions */
#define SMMU_BASE 0x05000000 /* GR0 Base */
-/* DCFG - GUR */
-
/* Cache Coherent Interconnect */
#define CCI_MN_BASE 0x04000000
#define CCI_MN_RNF_NODEID_LIST 0x180
@@ -134,8 +130,6 @@
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
-#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
-
/* DCFG - GUR */
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
@@ -165,8 +159,6 @@
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
-#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
-
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000
#define GICR_BASE 0x06200000
@@ -214,8 +206,6 @@
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
-#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
-
/* SEC */
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
@@ -89,6 +89,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
@@ -81,6 +81,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
@@ -84,6 +84,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
@@ -108,6 +108,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
@@ -103,6 +103,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
@@ -103,6 +103,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
@@ -78,6 +78,8 @@ CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
@@ -81,6 +81,8 @@ CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
@@ -100,6 +100,8 @@ CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
@@ -100,6 +100,8 @@ CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
@@ -77,6 +77,8 @@ CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
@@ -83,6 +83,8 @@ CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
@@ -81,6 +81,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
@@ -84,6 +84,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
@@ -97,6 +97,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
@@ -77,6 +77,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
@@ -91,6 +91,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
@@ -80,6 +80,8 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0x580980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME_PCI=y
@@ -83,6 +83,8 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0x580980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME_PCI=y
@@ -102,6 +102,8 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0x980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME_PCI=y
@@ -72,6 +72,8 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0x980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME_PCI=y
@@ -95,6 +95,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
@@ -71,6 +71,8 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0x980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
@@ -78,6 +78,8 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0x980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
@@ -86,6 +86,8 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
@@ -94,6 +94,8 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
@@ -82,6 +82,8 @@ CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
@@ -89,6 +89,8 @@ CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
@@ -75,6 +75,8 @@ CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
@@ -84,6 +84,8 @@ CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
@@ -84,6 +84,8 @@ CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
@@ -84,6 +84,8 @@ CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
@@ -92,6 +92,8 @@ CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
@@ -93,6 +93,8 @@ CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
@@ -71,6 +71,7 @@ CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_VITESSE=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
@@ -375,6 +375,7 @@ config SYS_QE_FMAN_FW_LENGTH
config SYS_FMAN_V3
bool
+ select FSL_MEMAC
help
SoC has FMan v3 with mEMAC
@@ -11,7 +11,6 @@ obj-y += tgec.o
obj-y += tgec_phy.o
# Soc have FMAN v3 with mEMAC
-obj-$(CONFIG_SYS_FMAN_V3) += memac_phy.o
obj-$(CONFIG_SYS_FMAN_V3) += memac.o
# SoC specific SERDES support
@@ -345,6 +345,13 @@ config PHY_NCSI
endif #PHYLIB
+config FSL_MEMAC
+ bool "NXP mEMAC PHY support"
+
+config SYS_MEMAC_LITTLE_ENDIAN
+ bool "mEMAC is access in little endian mode"
+ depends on FSL_MEMAC || FSL_LS_MDIO
+
config PHY_RESET_DELAY
int "Extra delay after reset before MII register access"
default 0
@@ -297,8 +297,6 @@
#endif
#endif
-#define CONFIG_FSL_MEMAC
-
#define COMMON_ENV \
"kernelheader_addr_r=0x80200000\0" \
"fdtheader_addr_r=0x80100000\0" \
@@ -467,7 +465,6 @@
#endif
#ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_FSL_MEMAC
#define RGMII_PHY1_ADDR 0x1
#define RGMII_PHY2_ADDR 0x2
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
@@ -202,8 +202,6 @@
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_FSL_MEMAC
-
#ifndef SPL_NO_ENV
/* Initial environment variables */
#ifdef CONFIG_TFABOOT
@@ -239,8 +239,6 @@
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_FSL_MEMAC
-
/* Initial environment variables */
#undef CONFIG_EXTRA_ENV_SETTINGS
#ifdef CONFIG_NXP_ESBC
@@ -385,7 +383,6 @@
#endif
#if defined(CONFIG_FSL_MC_ENET)
-#define CONFIG_FSL_MEMAC
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
@@ -226,8 +226,6 @@
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_FSL_MEMAC
-
#define BOOT_TARGET_DEVICES(func) \
func(USB, usb, 0) \
func(MMC, mmc, 0) \
@@ -10,8 +10,6 @@
#include <asm/arch/config.h>
#include <asm/arch/soc.h>
-#define CONFIG_FSL_MEMAC
-
#define CONFIG_SYS_FLASH_BASE 0x20000000
/* DDR */
This converts the following to Kconfig: CONFIG_FSL_MEMAC CONFIG_SYS_MEMAC_LITTLE_ENDIAN Signed-off-by: Tom Rini <trini@konsulko.com> --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 10 ---------- configs/ls1088aqds_defconfig | 2 ++ configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1088aqds_qspi_defconfig | 2 ++ configs/ls1088aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1088aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1088aqds_tfa_defconfig | 2 ++ configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1088ardb_qspi_defconfig | 2 ++ configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1088ardb_sdcard_qspi_defconfig | 2 ++ configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1088ardb_tfa_defconfig | 2 ++ configs/ls2080aqds_SECURE_BOOT_defconfig | 2 ++ configs/ls2080aqds_defconfig | 2 ++ configs/ls2080aqds_nand_defconfig | 2 ++ configs/ls2080aqds_qspi_defconfig | 2 ++ configs/ls2080aqds_sdcard_defconfig | 2 ++ configs/ls2080ardb_SECURE_BOOT_defconfig | 2 ++ configs/ls2080ardb_defconfig | 2 ++ configs/ls2080ardb_nand_defconfig | 2 ++ configs/ls2081ardb_defconfig | 2 ++ configs/ls2088aqds_tfa_defconfig | 2 ++ configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls2088ardb_qspi_defconfig | 2 ++ configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls2088ardb_tfa_defconfig | 2 ++ configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/lx2160aqds_tfa_defconfig | 2 ++ configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/lx2160ardb_tfa_defconfig | 2 ++ configs/lx2160ardb_tfa_stmm_defconfig | 2 ++ configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/lx2162aqds_tfa_defconfig | 2 ++ configs/lx2162aqds_tfa_verified_boot_defconfig | 2 ++ configs/ten64_tfa_defconfig | 1 + drivers/net/Kconfig | 1 + drivers/net/fm/Makefile | 1 - drivers/net/phy/Kconfig | 7 +++++++ include/configs/ls1088aqds.h | 3 --- include/configs/ls1088ardb.h | 2 -- include/configs/ls2080aqds.h | 3 --- include/configs/ls2080ardb.h | 2 -- include/configs/lx2160a_common.h | 2 -- 44 files changed, 77 insertions(+), 23 deletions(-)