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bh=l38pLH8rfFDE8+/9rQN5Plfojjj2nBpxlHlW1fvonrI=; b=jy9GF3CNsldXqNTQNOviJU/JWcPuZp33onfddbhaW1D7t9u24T2bSO8IcH9EqbJSQ0 mXgl+KxBlPAkfKxZGHRWoAnbNvO6WjfDD0P97hDoeFA1do/LQAHcaI1Lx3NVPEh2nCmv T89HT3S1sWs69vJI+wrS+XyXiWmzuRJDvSSaIhqz2BALO1aqlXoTixQ0o4klI09Mgbgi A9A5S4XRXvp3+nZPi8V0pGVOR7pk39DNKX6Twp7TVnQAugcU8w77KO1jmTxke5qVn8MS mfIbp40bzXT8NrTcwTdEOhAXp3qzcQmiG3vpKV7avjugCF+ehoxxsHeHzforUQHLDlH+ XBaA== X-Gm-Message-State: AJIora+V1WRjA0L0QBTeWpT9KSyKv84ulQujh7CvAO3SssskS6w9BA3v isk/B1qXcwb8xWcCNdpwK1M= X-Google-Smtp-Source: AGRyM1uA5CWZkL+aw5mQr+/p0UAP0fs3xxGmEH3Ee00MmiQtNleXXFtexYXk8dxcDdUluXDLAmrUHg== X-Received: by 2002:a17:902:e888:b0:16a:1b3d:aac4 with SMTP id w8-20020a170902e88800b0016a1b3daac4mr27999567plg.80.1656059087667; Fri, 24 Jun 2022 01:24:47 -0700 (PDT) Received: from localhost.localdomain ([112.78.84.36]) by smtp.gmail.com with ESMTPSA id a4-20020a170902710400b00162037fbb68sm1151414pll.215.2022.06.24.01.24.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jun 2022 01:24:47 -0700 (PDT) From: Jim Liu X-Google-Original-From: Jim Liu To: sean.anderson@seco.com, trini@konsulko.com, sjg@chromium.org, tharvey@gateworks.com, pali@kernel.org, YSCHU@nuvoton.com, KWLIU@nuvoton.com, JJLIU0@nuvoton.com Cc: u-boot@lists.denx.de Subject: [PATCH v2] misc: nuvoton: Add host interface configuartion driver Date: Fri, 24 Jun 2022 16:24:37 +0800 Message-Id: <20220624082437.16650-1-JJLIU0@nuvoton.com> X-Mailer: git-send-email 2.17.1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean add nuvoton BMC npcm750 host configuartion driver Signed-off-by: Jim Liu --- Changes for v2: - add kconfig and use depend for kconfig --- drivers/misc/Kconfig | 6 ++ drivers/misc/Makefile | 1 + drivers/misc/npcm_host_intf.c | 110 ++++++++++++++++++++++++++++++++++ 3 files changed, 117 insertions(+) create mode 100644 drivers/misc/npcm_host_intf.c diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 85ae7f62e9..265a7e510d 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -282,6 +282,12 @@ config MXC_OCOTP Programmable memory pages that are stored on the some Freescale i.MX processors. +config NPCM_HOST + bool "Enable support espi or LPC for Host" + depends on REGMAP && SYSCON + help + Enable NPCM BMC espi or LPC support for Host reading and writing. + config SPL_MXC_OCOTP bool "Enable MXC OCOTP driver in SPL" depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610) diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 7a6047f64f..51a534d535 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -53,6 +53,7 @@ obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o obj-$(CONFIG_$(SPL_)MXC_OCOTP) += mxc_ocotp.o obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o +obj-$(CONFIG_NPCM_HOST) += npcm_host_intf.o obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o obj-$(CONFIG_P2SB) += p2sb-uclass.o obj-$(CONFIG_PCA9551_LED) += pca9551_led.o diff --git a/drivers/misc/npcm_host_intf.c b/drivers/misc/npcm_host_intf.c new file mode 100644 index 0000000000..0244e40457 --- /dev/null +++ b/drivers/misc/npcm_host_intf.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Host interface (LPC or eSPI) configuration on Nuvoton BMC + * Copyright (c) 2022 Nuvoton Technology Corp. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define SMC_CTL_REG_ADDR 0xc0001001 +#define SMC_CTL_HOSTWAIT 0x80 + +/* GCR Register Offsets */ +#define HIFCR 0x50 +#define MFSEL1 0x260 +#define MFSEL4 0x26c + +/* ESPI Register offsets */ +#define ESPICFG 0x4 +#define ESPIHINDP 0x80 + +/* MFSEL bit fileds */ +#define MFSEL1_LPCSEL BIT(26) +#define MFSEL4_ESPISEL BIT(8) + +/* ESPICFG bit fileds */ +#define CHSUPP_MASK GENMASK(27, 24) +#define IOMODE_MASK GENMASK(9, 8) +#define IOMODE_SDQ FIELD_PREP(IOMODE_MASK, 3) +#define MAXFREQ_MASK GENMASK(12, 10) +#define MAXFREQ_33MHZ FIELD_PREP(MAXFREQ_MASK, 2) + +/* ESPIHINDP bit fileds */ +#define AUTO_SBLD BIT(4) +#define AUTO_HS1 BIT(8) +#define AUTO_HS2 BIT(12) +#define AUTO_HS3 BIT(16) + +static int npcm_host_intf_bind(struct udevice *dev) +{ + struct regmap *syscon; + void __iomem *base; + u32 ch_supp, val; + u32 ioaddr; + const char *type; + int ret; + + /* Release host wait */ + setbits_8(SMC_CTL_REG_ADDR, SMC_CTL_HOSTWAIT); + + syscon = syscon_regmap_lookup_by_phandle(dev, "syscon"); + if (IS_ERR(syscon)) { + dev_err(dev, "%s: unable to get syscon, dev %s\n", __func__, dev->name); + return PTR_ERR(syscon); + } + + ioaddr = dev_read_u32_default(dev, "ioaddr", 0); + if (ioaddr) + regmap_write(syscon, HIFCR, ioaddr); + + type = dev_read_string(dev, "type"); + if (!type) + return -EINVAL; + + if (!strcmp(type, "espi")) { + base = dev_read_addr_ptr(dev); + if (!base) + return -EINVAL; + + ret = dev_read_u32(dev, "channel-support", &ch_supp); + if (ret) + return ret; + + /* Select eSPI pins function */ + regmap_update_bits(syscon, MFSEL1, MFSEL1_LPCSEL, 0); + regmap_update_bits(syscon, MFSEL4, MFSEL4_ESPISEL, MFSEL4_ESPISEL); + + val = AUTO_SBLD | AUTO_HS1 | AUTO_HS2 | AUTO_HS3 | ch_supp; + writel(val, base + ESPIHINDP); + + val = readl(base + ESPICFG); + val &= ~(CHSUPP_MASK | IOMODE_MASK | MAXFREQ_MASK); + val |= IOMODE_SDQ | MAXFREQ_33MHZ | FIELD_PREP(CHSUPP_MASK, ch_supp); + writel(val, base + ESPICFG); + } else if (!strcmp(type, "lpc")) { + /* Select LPC pin function */ + regmap_update_bits(syscon, MFSEL4, MFSEL4_ESPISEL, 0); + regmap_update_bits(syscon, MFSEL1, MFSEL1_LPCSEL, MFSEL1_LPCSEL); + } + + return 0; +} + +static const struct udevice_id npcm_hostintf_ids[] = { + { .compatible = "nuvoton,npcm750-host-intf" }, + { .compatible = "nuvoton,npcm845-host-intf" }, + { } +}; + +U_BOOT_DRIVER(npcm_host_intf) = { + .name = "npcm_host_intf", + .id = UCLASS_MISC, + .of_match = npcm_hostintf_ids, + .bind = npcm_host_intf_bind, +};