Message ID | 20220430124317.17382-8-peng.fan@oss.nxp.com |
---|---|
State | Superseded |
Delegated to: | Stefano Babic |
Headers | show |
Series | imx8m: convert to DM_SERIAL | expand |
Hello Peng, Am Samstag, dem 30.04.2022 um 20:43 +0800 schrieb Peng Fan (OSS): > From: Peng Fan <peng.fan@nxp.com> > > Enable CONFIG_DM_SERIAL. uart and its pinmux was already > marked with u-boot,dm-spl. > Move preloader_console_init after spl_early_init to make sure driver > model work. thank you for the patch. Works for phyCORE-i.MX8MM and phyCORE-i.MX8MP. Tested-by: Teresa Remmet <t.remmet@phytec.de> Regards, Teresa > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > board/phytec/phycore_imx8mm/spl.c | 12 ++---------- > board/phytec/phycore_imx8mp/spl.c | 8 -------- > configs/phycore-imx8mm_defconfig | 1 + > configs/phycore-imx8mp_defconfig | 1 + > include/configs/phycore_imx8mm.h | 3 --- > include/configs/phycore_imx8mp.h | 3 --- > 6 files changed, 4 insertions(+), 24 deletions(-) > > diff --git a/board/phytec/phycore_imx8mm/spl.c > b/board/phytec/phycore_imx8mm/spl.c > index d54145ef995..7f24a3affc8 100644 > --- a/board/phytec/phycore_imx8mm/spl.c > +++ b/board/phytec/phycore_imx8mm/spl.c > @@ -57,14 +57,8 @@ int board_fit_config_name_match(const char *name) > return 0; > } > > -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) > #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE) > > -static iomux_v3_cfg_t const uart_pads[] = { > - IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL), > - IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL), > -}; > - > static iomux_v3_cfg_t const wdog_pads[] = { > IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | > MUX_PAD_CTRL(WDOG_PAD_CTRL), > }; > @@ -77,8 +71,6 @@ int board_early_init_f(void) > > set_wdog_reset(wdog); > > - imx_iomux_v3_setup_multiple_pads(uart_pads, > ARRAY_SIZE(uart_pads)); > - > return 0; > } > > @@ -92,8 +84,6 @@ void board_init_f(ulong dummy) > > board_early_init_f(); > > - preloader_console_init(); > - > /* Clear the BSS. */ > memset(__bss_start, 0, __bss_end - __bss_start); > > @@ -103,6 +93,8 @@ void board_init_f(ulong dummy) > hang(); > } > > + preloader_console_init(); > + > enable_tzc380(); > > /* DDR initialization */ > diff --git a/board/phytec/phycore_imx8mp/spl.c > b/board/phytec/phycore_imx8mp/spl.c > index 19c486e5517..38a581bef57 100644 > --- a/board/phytec/phycore_imx8mp/spl.c > +++ b/board/phytec/phycore_imx8mp/spl.c > @@ -89,14 +89,8 @@ int board_fit_config_name_match(const char *name) > return 0; > } > > -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) > #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | > PAD_CTL_PE) > > -static iomux_v3_cfg_t const uart_pads[] = { > - MX8MP_PAD_UART1_RXD__UART1_DCE_RX | > MUX_PAD_CTRL(UART_PAD_CTRL), > - MX8MP_PAD_UART1_TXD__UART1_DCE_TX | > MUX_PAD_CTRL(UART_PAD_CTRL), > -}; > - > static iomux_v3_cfg_t const wdog_pads[] = { > MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | > MUX_PAD_CTRL(WDOG_PAD_CTRL), > }; > @@ -109,8 +103,6 @@ int board_early_init_f(void) > > set_wdog_reset(wdog); > > - imx_iomux_v3_setup_multiple_pads(uart_pads, > ARRAY_SIZE(uart_pads)); > - > return 0; > } > > diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore- > imx8mm_defconfig > index ba5833f7060..9da222afc54 100644 > --- a/configs/phycore-imx8mm_defconfig > +++ b/configs/phycore-imx8mm_defconfig > @@ -107,6 +107,7 @@ CONFIG_PINCTRL_IMX8M=y > CONFIG_DM_REGULATOR=y > CONFIG_DM_REGULATOR_FIXED=y > CONFIG_DM_REGULATOR_GPIO=y > +CONFIG_DM_SERIAL=y > CONFIG_MXC_UART=y > CONFIG_SPI=y > CONFIG_DM_SPI=y > diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore- > imx8mp_defconfig > index 86d0f4df7f6..a851b1bdccb 100644 > --- a/configs/phycore-imx8mp_defconfig > +++ b/configs/phycore-imx8mp_defconfig > @@ -98,6 +98,7 @@ CONFIG_DM_REGULATOR=y > CONFIG_DM_REGULATOR_FIXED=y > CONFIG_DM_REGULATOR_GPIO=y > CONFIG_SPL_POWER_I2C=y > +CONFIG_DM_SERIAL=y > CONFIG_MXC_UART=y > CONFIG_SYSRESET=y > CONFIG_SPL_SYSRESET=y > diff --git a/include/configs/phycore_imx8mm.h > b/include/configs/phycore_imx8mm.h > index 71f0c42ec0c..564b8125ba3 100644 > --- a/include/configs/phycore_imx8mm.h > +++ b/include/configs/phycore_imx8mm.h > @@ -83,9 +83,6 @@ > #define PHYS_SDRAM 0x40000000 > #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ > > -/* UART */ > -#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR > - > /* Monitor Command Prompt */ > #define CONFIG_SYS_CBSIZE SZ_2K > #define CONFIG_SYS_MAXARGS 64 > diff --git a/include/configs/phycore_imx8mp.h > b/include/configs/phycore_imx8mp.h > index 0c963b62b3b..3e4315f2b81 100644 > --- a/include/configs/phycore_imx8mp.h > +++ b/include/configs/phycore_imx8mp.h > @@ -83,9 +83,6 @@ > #define PHYS_SDRAM 0x40000000 > #define PHYS_SDRAM_SIZE 0x80000000 > > -/* UART */ > -#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR > - > /* Monitor Command Prompt */ > #define CONFIG_SYS_CBSIZE SZ_2K > #define CONFIG_SYS_MAXARGS 64
diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c index d54145ef995..7f24a3affc8 100644 --- a/board/phytec/phycore_imx8mm/spl.c +++ b/board/phytec/phycore_imx8mm/spl.c @@ -57,14 +57,8 @@ int board_fit_config_name_match(const char *name) return 0; } -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE) -static iomux_v3_cfg_t const uart_pads[] = { - IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -77,8 +71,6 @@ int board_early_init_f(void) set_wdog_reset(wdog); - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - return 0; } @@ -92,8 +84,6 @@ void board_init_f(ulong dummy) board_early_init_f(); - preloader_console_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); @@ -103,6 +93,8 @@ void board_init_f(ulong dummy) hang(); } + preloader_console_init(); + enable_tzc380(); /* DDR initialization */ diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index 19c486e5517..38a581bef57 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -89,14 +89,8 @@ int board_fit_config_name_match(const char *name) return 0; } -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) -static iomux_v3_cfg_t const uart_pads[] = { - MX8MP_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX8MP_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_pads[] = { MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -109,8 +103,6 @@ int board_early_init_f(void) set_wdog_reset(wdog); - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - return 0; } diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index ba5833f7060..9da222afc54 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -107,6 +107,7 @@ CONFIG_PINCTRL_IMX8M=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 86d0f4df7f6..a851b1bdccb 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -98,6 +98,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_POWER_I2C=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index 71f0c42ec0c..564b8125ba3 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -83,9 +83,6 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ -/* UART */ -#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 0c963b62b3b..3e4315f2b81 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -83,9 +83,6 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 -/* UART */ -#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K #define CONFIG_SYS_MAXARGS 64