From patchwork Wed Mar 30 10:06:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 1611017 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=SX9oxVQ6; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KT2Gk3MNRz9sFk for ; Wed, 30 Mar 2022 21:09:34 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C7FF4840EC; Wed, 30 Mar 2022 12:08:43 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1648634924; bh=oZZ62AAD9xD1ySWYMIsSDSyKtaKc4DOKEbq/k7PvW6w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=SX9oxVQ69Y0S25RiM2KYlpWAOHKqZ37rhi+sOC85HkbU4jrnSKis3SpVJRgj65uuH YhbvJM4G1YNzc743HbD7O6ij0SsHMzsCOl7NF02m4X4YoKVtL5JD3hp0numCqE0quY jyDlhpi5ZCmKptfR3JkOpMjnytnPFgtXe8UKJd5KFP+yeRJdqxUvEuHqA2Bs1g3Lu2 riCQebrOIJNE58297rqogX3HG+V57b3rZM9K30VcLegrMY8U3O3QekgFCQVXUgbgtI VbhAK+qWq0DzQy7HHw5Bx6QuBqR93JyV+yvIsBH6nfbUA+y5PaLnYhZtt04MGnJcDN HkjpI0Aep6VZQ== Received: by phobos.denx.de (Postfix, from userid 109) id EC2A1840B2; Wed, 30 Mar 2022 12:07:59 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, T_SCC_BODY_TEXT_LINE,T_SPF_TEMPERROR autolearn=ham autolearn_force=no version=3.4.2 Received: from mout-u-107.mailbox.org (mout-u-107.mailbox.org [91.198.250.252]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 29B11840CF for ; Wed, 30 Mar 2022 12:07:40 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sr@denx.de Received: from smtp102.mailbox.org (unknown [91.198.250.119]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-107.mailbox.org (Postfix) with ESMTPS id 4KT2DW4jClz9sR9; Wed, 30 Mar 2022 12:07:39 +0200 (CEST) From: Stefan Roese To: u-boot@lists.denx.de Cc: awilliams@marvell.com, cchavva@marvell.com Subject: [PATCH 04/52] mips: octeon: Add cvmx-lbk-defs.h header file Date: Wed, 30 Mar 2022 12:06:40 +0200 Message-Id: <20220330100728.871561-5-sr@denx.de> In-Reply-To: <20220330100728.871561-1-sr@denx.de> References: <20220330100728.871561-1-sr@denx.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean From: Aaron Williams Import cvmx-lbk-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams Signed-off-by: Stefan Roese --- .../mach-octeon/include/mach/cvmx-lbk-defs.h | 157 ++++++++++++++++++ 1 file changed, 157 insertions(+) create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-lbk-defs.h diff --git a/arch/mips/mach-octeon/include/mach/cvmx-lbk-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-lbk-defs.h new file mode 100644 index 000000000000..1068a19ad80b --- /dev/null +++ b/arch/mips/mach-octeon/include/mach/cvmx-lbk-defs.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018-2022 Marvell International Ltd. + * + * Configuration and status register (CSR) type definitions for + * Octeon lbk. + */ + +#ifndef __CVMX_LBK_DEFS_H__ +#define __CVMX_LBK_DEFS_H__ + +#define CVMX_LBK_BIST_RESULT (0x0001180012000020ull) +#define CVMX_LBK_CHX_PKIND(offset) (0x0001180012000200ull + ((offset) & 63) * 8) +#define CVMX_LBK_CLK_GATE_CTL (0x0001180012000008ull) +#define CVMX_LBK_DAT_ERR_INFO (0x0001180012000050ull) +#define CVMX_LBK_ECC_CFG (0x0001180012000060ull) +#define CVMX_LBK_INT (0x0001180012000040ull) +#define CVMX_LBK_SFT_RST (0x0001180012000000ull) + +/** + * cvmx_lbk_bist_result + * + * This register provides access to the internal BIST results. Each bit is the + * BIST result of an individual memory (per bit, 0 = pass and 1 = fail). + */ +union cvmx_lbk_bist_result { + u64 u64; + struct cvmx_lbk_bist_result_s { + u64 reserved_1_63 : 63; + u64 dat : 1; + } s; + struct cvmx_lbk_bist_result_s cn73xx; + struct cvmx_lbk_bist_result_s cn78xx; + struct cvmx_lbk_bist_result_s cn78xxp1; + struct cvmx_lbk_bist_result_s cnf75xx; +}; + +typedef union cvmx_lbk_bist_result cvmx_lbk_bist_result_t; + +/** + * cvmx_lbk_ch#_pkind + */ +union cvmx_lbk_chx_pkind { + u64 u64; + struct cvmx_lbk_chx_pkind_s { + u64 reserved_6_63 : 58; + u64 pkind : 6; + } s; + struct cvmx_lbk_chx_pkind_s cn73xx; + struct cvmx_lbk_chx_pkind_s cn78xx; + struct cvmx_lbk_chx_pkind_s cn78xxp1; + struct cvmx_lbk_chx_pkind_s cnf75xx; +}; + +typedef union cvmx_lbk_chx_pkind cvmx_lbk_chx_pkind_t; + +/** + * cvmx_lbk_clk_gate_ctl + * + * This register is for diagnostic use only. + * + */ +union cvmx_lbk_clk_gate_ctl { + u64 u64; + struct cvmx_lbk_clk_gate_ctl_s { + u64 reserved_1_63 : 63; + u64 dis : 1; + } s; + struct cvmx_lbk_clk_gate_ctl_s cn73xx; + struct cvmx_lbk_clk_gate_ctl_s cn78xx; + struct cvmx_lbk_clk_gate_ctl_s cn78xxp1; + struct cvmx_lbk_clk_gate_ctl_s cnf75xx; +}; + +typedef union cvmx_lbk_clk_gate_ctl cvmx_lbk_clk_gate_ctl_t; + +/** + * cvmx_lbk_dat_err_info + */ +union cvmx_lbk_dat_err_info { + u64 u64; + struct cvmx_lbk_dat_err_info_s { + u64 reserved_58_63 : 6; + u64 dbe_ecc_out : 9; + u64 dbe_synd : 9; + u64 dbe_addr : 8; + u64 reserved_26_31 : 6; + u64 sbe_ecc_out : 9; + u64 sbe_synd : 9; + u64 sbe_addr : 8; + } s; + struct cvmx_lbk_dat_err_info_s cn73xx; + struct cvmx_lbk_dat_err_info_s cn78xx; + struct cvmx_lbk_dat_err_info_s cn78xxp1; + struct cvmx_lbk_dat_err_info_s cnf75xx; +}; + +typedef union cvmx_lbk_dat_err_info cvmx_lbk_dat_err_info_t; + +/** + * cvmx_lbk_ecc_cfg + */ +union cvmx_lbk_ecc_cfg { + u64 u64; + struct cvmx_lbk_ecc_cfg_s { + u64 reserved_3_63 : 61; + u64 dat_flip : 2; + u64 dat_cdis : 1; + } s; + struct cvmx_lbk_ecc_cfg_s cn73xx; + struct cvmx_lbk_ecc_cfg_s cn78xx; + struct cvmx_lbk_ecc_cfg_s cn78xxp1; + struct cvmx_lbk_ecc_cfg_s cnf75xx; +}; + +typedef union cvmx_lbk_ecc_cfg cvmx_lbk_ecc_cfg_t; + +/** + * cvmx_lbk_int + */ +union cvmx_lbk_int { + u64 u64; + struct cvmx_lbk_int_s { + u64 reserved_6_63 : 58; + u64 chan_oflow : 1; + u64 chan_uflow : 1; + u64 dat_oflow : 1; + u64 dat_uflow : 1; + u64 dat_dbe : 1; + u64 dat_sbe : 1; + } s; + struct cvmx_lbk_int_s cn73xx; + struct cvmx_lbk_int_s cn78xx; + struct cvmx_lbk_int_s cn78xxp1; + struct cvmx_lbk_int_s cnf75xx; +}; + +typedef union cvmx_lbk_int cvmx_lbk_int_t; + +/** + * cvmx_lbk_sft_rst + */ +union cvmx_lbk_sft_rst { + u64 u64; + struct cvmx_lbk_sft_rst_s { + u64 reserved_1_63 : 63; + u64 reset : 1; + } s; + struct cvmx_lbk_sft_rst_s cn73xx; + struct cvmx_lbk_sft_rst_s cn78xx; + struct cvmx_lbk_sft_rst_s cn78xxp1; + struct cvmx_lbk_sft_rst_s cnf75xx; +}; + +typedef union cvmx_lbk_sft_rst cvmx_lbk_sft_rst_t; + +#endif