@@ -523,6 +523,7 @@ config ARCH_P2020
config ARCH_P2041
bool
+ select BACKSIDE_L2_CACHE
select E500MC
select FSL_LAW
select SYS_CACHE_SHIFT_6
@@ -548,6 +549,7 @@ config ARCH_P2041
config ARCH_P3041
bool
+ select BACKSIDE_L2_CACHE
select E500MC
select FSL_LAW
select SYS_CACHE_SHIFT_6
@@ -578,6 +580,7 @@ config ARCH_P3041
config ARCH_P4080
bool
+ select BACKSIDE_L2_CACHE
select E500MC
select FSL_LAW
select SYS_CACHE_SHIFT_6
@@ -617,6 +620,7 @@ config ARCH_P4080
config ARCH_P5040
bool
+ select BACKSIDE_L2_CACHE
select E500MC
select FSL_LAW
select SYS_CACHE_SHIFT_6
@@ -647,6 +651,7 @@ config ARCH_QEMU_E500
config ARCH_T1024
bool
+ select BACKSIDE_L2_CACHE
select E500MC
select FSL_LAW
select SYS_CACHE_SHIFT_6
@@ -670,6 +675,7 @@ config ARCH_T1024
config ARCH_T1040
bool
+ select BACKSIDE_L2_CACHE
select E500MC
select FSL_LAW
select SYS_CACHE_SHIFT_6
@@ -693,6 +699,7 @@ config ARCH_T1040
config ARCH_T1042
bool
+ select BACKSIDE_L2_CACHE
select E500MC
select FSL_LAW
select SYS_CACHE_SHIFT_6
@@ -1108,6 +1115,9 @@ config SYS_NUM_TLBCAMS
Number of TLB CAM entries for Book-E chips. 64 for E500MC,
16 for other E500 SoCs.
+config BACKSIDE_L2_CACHE
+ bool
+
config SYS_PPC64
bool
@@ -56,7 +56,6 @@
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_ENABLE_36BIT_PHYS
@@ -119,7 +119,6 @@
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
@@ -96,7 +96,6 @@
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
@@ -57,7 +57,6 @@
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
@@ -150,7 +150,6 @@
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_ENABLE_36BIT_PHYS
This converts the following to Kconfig: CONFIG_BACKSIDE_L2_CACHE Signed-off-by: Tom Rini <trini@konsulko.com> --- arch/powerpc/cpu/mpc85xx/Kconfig | 10 ++++++++++ include/configs/P2041RDB.h | 1 - include/configs/T102xRDB.h | 1 - include/configs/T104xRDB.h | 1 - include/configs/corenet_ds.h | 1 - include/configs/kmcent2.h | 1 - 6 files changed, 10 insertions(+), 5 deletions(-)