Message ID | 20220303235239.28630-7-jbx6244@gmail.com |
---|---|
State | Superseded |
Delegated to: | Kever Yang |
Headers | show |
Series | [v3,01/12] rockchip: rk3228-power: sync power domain dt-binding header from Linux | expand |
On 2022/3/4 07:52, Johan Jonker wrote: > In order to update the DT for rk3288 > sync the clock dt-binding header. > This is the state as of v5.17 in Linux. > Keep SCLK_MAC_PLL in use for rk3288 clock driver. > > Signed-off-by: Johan Jonker <jbx6244@gmail.com> > Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Thanks, - Kever > --- > include/dt-bindings/clock/rk3288-cru.h | 13 ++++++++++++- > 1 file changed, 12 insertions(+), 1 deletion(-) > > diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h > index e368d767..453f6671 100644 > --- a/include/dt-bindings/clock/rk3288-cru.h > +++ b/include/dt-bindings/clock/rk3288-cru.h > @@ -1,9 +1,12 @@ > -/* SPDX-License-Identifier: GPL-2.0+ */ > +/* SPDX-License-Identifier: GPL-2.0-or-later */ > /* > * Copyright (c) 2014 MundoReader S.L. > * Author: Heiko Stuebner <heiko@sntech.de> > */ > > +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H > +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H > + > /* core clocks */ > #define PLL_APLL 1 > #define PLL_DPLL 2 > @@ -74,6 +77,9 @@ > #define SCLK_USBPHY480M_SRC 122 > #define SCLK_PVTM_CORE 123 > #define SCLK_PVTM_GPU 124 > +#define SCLK_CRYPTO 125 > +#define SCLK_MIPIDSI_24M 126 > +#define SCLK_VIP_OUT 127 > > #define SCLK_MAC_PLL 150 > #define SCLK_MAC 151 > @@ -153,6 +159,9 @@ > #define PCLK_DDRUPCTL1 366 > #define PCLK_PUBL1 367 > #define PCLK_WDT 368 > +#define PCLK_EFUSE256 369 > +#define PCLK_EFUSE1024 370 > +#define PCLK_ISP_IN 371 > > /* hclk gates */ > #define HCLK_GPS 448 > @@ -368,3 +377,5 @@ > #define SRST_TSP_CLKIN0 189 > #define SRST_TSP_CLKIN1 190 > #define SRST_TSP_27M 191 > + > +#endif
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h index e368d767..453f6671 100644 --- a/include/dt-bindings/clock/rk3288-cru.h +++ b/include/dt-bindings/clock/rk3288-cru.h @@ -1,9 +1,12 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner <heiko@sntech.de> */ +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H + /* core clocks */ #define PLL_APLL 1 #define PLL_DPLL 2 @@ -74,6 +77,9 @@ #define SCLK_USBPHY480M_SRC 122 #define SCLK_PVTM_CORE 123 #define SCLK_PVTM_GPU 124 +#define SCLK_CRYPTO 125 +#define SCLK_MIPIDSI_24M 126 +#define SCLK_VIP_OUT 127 #define SCLK_MAC_PLL 150 #define SCLK_MAC 151 @@ -153,6 +159,9 @@ #define PCLK_DDRUPCTL1 366 #define PCLK_PUBL1 367 #define PCLK_WDT 368 +#define PCLK_EFUSE256 369 +#define PCLK_EFUSE1024 370 +#define PCLK_ISP_IN 371 /* hclk gates */ #define HCLK_GPS 448 @@ -368,3 +377,5 @@ #define SRST_TSP_CLKIN0 189 #define SRST_TSP_CLKIN1 190 #define SRST_TSP_27M 191 + +#endif