diff mbox series

[6/7] microblaze: exception: fix unaligned data access register mask

Message ID 20220213080925.1548411-6-ovidiu.panait@windriver.com
State Accepted
Commit d1114b83405ceaccd46bce96001e6da4fab3ae40
Delegated to: Michal Simek
Headers show
Series [1/7] microblaze: exception: move privileged instruction exception out of v5 ifdef | expand

Commit Message

Ovidiu Panait Feb. 13, 2022, 8:09 a.m. UTC 
The correct mask for getting the source/destination register from ESR in
the case of an unaligned access exception is 0x3E0. With this change, a
dummy unaligned store produces the expected info:
"""
>> swi r5, r0, 0x111

 ...
 Hardware exception at 0x111 address
 Unaligned data access exception
 Unaligned word access
 Unaligned store access
 Register R5
 Return address from exception 0x7f99dfc
 ### ERROR ### Please RESET the board ###
"""

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
---

 arch/microblaze/cpu/exception.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c
index d37f04364a..d3640d3903 100644
--- a/arch/microblaze/cpu/exception.c
+++ b/arch/microblaze/cpu/exception.c
@@ -38,7 +38,7 @@  void _hw_exception_handler (void)
 
 		printf("Unaligned %sword access\n", ((state & 0x800) ? "" : "half"));
 		printf("Unaligned %s access\n", ((state & 0x400) ? "store" : "load"));
-		printf("Register R%x\n", (state & 0x3E) >> 5);
+		printf("Register R%x\n", (state & 0x3E0) >> 5);
 		break;
 	case 0x2:
 		puts("Illegal op-code exception\n");