From patchwork Fri Jan 28 22:42:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alper Nebi Yasak X-Patchwork-Id: 1585989 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=hYvRPL6n; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Jlsv30VYDz9t3b for ; Sat, 29 Jan 2022 09:43:43 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CC44683855; Fri, 28 Jan 2022 23:43:24 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="hYvRPL6n"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 51EF48380F; Fri, 28 Jan 2022 23:43:23 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id AF36C83855 for ; Fri, 28 Jan 2022 23:43:20 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=alpernebiyasak@gmail.com Received: by mail-wr1-x42e.google.com with SMTP id l25so13459442wrb.13 for ; Fri, 28 Jan 2022 14:43:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UMxO/ZdprjKbKXlpRtxYj+8eHSvboo5T23aQ5IzVgyA=; b=hYvRPL6nq9r8/cnHsspIoeYnQ7nu8Ok0I3UjjDqwLMGO6DFt2QxaLRWbJwq8kavACm J4kc5oRqF3zkZd1+vBepsvmg3pIMrhlY7QXBu85xyaeWzlc2njOC2X94eyK7huXehCiI 97n7+RuzDP0Wrc4zfJA8fSzd+Farjkq+Roq89ATLOcRDAoloUeJ059qg14H1rPr+xyoy O2tGbi3V0xafEZzj+WzDn865QiV0GHoqY0sYM3y6pUCP46V3QMB2t2bVmz9Os0cK8E9p z0V+OP/fnxBemX+Zm/va0FzrvgLDGLq3YQ4c1QqxUwN9Ew03j4x93qMAlvszQq8cLdoM AWhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UMxO/ZdprjKbKXlpRtxYj+8eHSvboo5T23aQ5IzVgyA=; b=MbgQN/L0MBlcrRHjjtmxhs/Do5cin+lq+A/KVgYgTo9kFMin38DSZsaVyKHE1g/L7Z tOsg75U88NcGnQi81xdBij6hxawKzl1CbanCNe2xidMhkHxUC1jki9HBxeDfkSNzc8OP pJGHdbI4FP6h97f4glyl5njMjVqXv7RXuwTLMsGRmoKCsD21WexWkLKni0nBCEnBEDzm L+HvPPUiMN7+U5ML4QTzvQeNQY4bKyzzSPtOZaLxp81wnTXiRyBFIlgHA4coZUX19idD i6eaH5nKKQ2qnPm4Vm16LDSGHsMLYaDrKWgI53dAMsmmTIbMhZbF6jWbrvmV+hzC6xwR pPiQ== X-Gm-Message-State: AOAM533nsF0Qt++y7KaAWZAI0p+lide3C4Jy5cm/en7crvkuHM5wCpCS I3tS3ALCk/EIv1pzFIyc1lfnCe8d5nw4gg== X-Google-Smtp-Source: ABdhPJzaAio5jZeMX5lyDjQSVdcL45UDgu4l3CpSTjE8bmEIEZ3TXJB6DdqhcnmyM4t84ns2tr1kLw== X-Received: by 2002:a5d:698f:: with SMTP id g15mr8581938wru.273.1643409800265; Fri, 28 Jan 2022 14:43:20 -0800 (PST) Received: from localhost.localdomain ([178.233.26.119]) by smtp.gmail.com with ESMTPSA id m8sm5413586wrn.106.2022.01.28.14.43.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jan 2022 14:43:19 -0800 (PST) From: Alper Nebi Yasak To: u-boot@lists.denx.de Cc: Jack Mitchell , Kever Yang , Heinrich Schuchardt , Yifeng Zhao , Samuel Dionne-Riel , Simon Glass , Aswath Govindraju , Philipp Tomsich , Ashok Reddy Soma , Stephen Carlson , Jaehoon Chung , Michal Simek , Faiz Abbas , Jagan Teki , Peng Fan , Peter Robinson , Alper Nebi Yasak Subject: [PATCH v4 4/4] rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3568 Date: Sat, 29 Jan 2022 01:42:39 +0300 Message-Id: <20220128224240.4226-5-alpernebiyasak@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220128224240.4226-1-alpernebiyasak@gmail.com> References: <20220128224240.4226-1-alpernebiyasak@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On RK3568, a register bit must be set to enable Enhanced Strobe. However, it appears that the address of this register may differ from vendor to vendor and should be read from the underlying MMC IP. Let the Rockchip SDHCI driver read this address and set the relevant bit when Enhanced Strobe configuration is requested. Additionally, a bit signifying that the connected hardware is an eMMC chip must be set to enable Data Strobe for HS400 and HS400ES modes. Also make the driver set this bit as appropriate. This is partly ported from Linux's Synopsys DWC MSHC driver which happens to be the underlying IP. (drivers/mmc/host/sdhci-of-dwcmshc.c in Linux tree). Signed-off-by: Alper Nebi Yasak Reviewed-by: Jaehoon Chung --- Only build-tested as I don't have a RK3568 board. (no changes since v3) Changes in v3: - Set DWCMSHC_CARD_IS_EMMC bit in rk3568_emmc_phy_init() Changes in v2: - Rename rk3568_set_enhanced_strobe -> rk3568_sdhci_set_enhanced_strobe - Let set_enhanced_strobe() unset the ES bit if mode is not HS400_ES drivers/mmc/rockchip_sdhci.c | 42 ++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index f4d5a59036a2..1d96c4696b6f 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -45,6 +45,14 @@ #define ARASAN_VENDOR_REGISTER 0x78 #define ARASAN_VENDOR_ENHANCED_STROBE BIT(0) +/* DWC IP vendor area 1 pointer */ +#define DWCMSHC_P_VENDOR_AREA1 0xe8 +#define DWCMSHC_AREA1_MASK GENMASK(11, 0) +/* Offset inside the vendor area 1 */ +#define DWCMSHC_EMMC_CONTROL 0x2c +#define DWCMSHC_CARD_IS_EMMC BIT(0) +#define DWCMSHC_ENHANCED_STROBE BIT(8) + /* Rockchip specific Registers */ #define DWCMSHC_EMMC_DLL_CTRL 0x800 #define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1) @@ -279,11 +287,25 @@ static int rk3568_emmc_phy_init(struct udevice *dev) { struct rockchip_sdhc *prv = dev_get_priv(dev); struct sdhci_host *host = &prv->host; + struct mmc *mmc = host->mmc; u32 extra; + u32 vendor; + int reg; extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); + /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 and HS400ES */ + reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK) + + DWCMSHC_EMMC_CONTROL; + + vendor = sdhci_readw(host, reg); + if (IS_MMC(mmc)) + vendor |= DWCMSHC_CARD_IS_EMMC; + else + vendor &= ~DWCMSHC_CARD_IS_EMMC; + sdhci_writew(host, vendor, reg); + return 0; } @@ -346,6 +368,25 @@ static int rk3568_emmc_get_phy(struct udevice *dev) return 0; } +static int rk3568_sdhci_set_enhanced_strobe(struct sdhci_host *host) +{ + struct mmc *mmc = host->mmc; + u32 vendor; + int reg; + + reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK) + + DWCMSHC_EMMC_CONTROL; + + vendor = sdhci_readl(host, reg); + if (mmc->selected_mode == MMC_HS_400_ES) + vendor |= DWCMSHC_ENHANCED_STROBE; + else + vendor &= ~DWCMSHC_ENHANCED_STROBE; + sdhci_writel(host, vendor, reg); + + return 0; +} + static int rk3568_sdhci_set_ios_post(struct sdhci_host *host) { struct mmc *mmc = host->mmc; @@ -554,6 +595,7 @@ static const struct sdhci_data rk3568_data = { .get_phy = rk3568_emmc_get_phy, .emmc_phy_init = rk3568_emmc_phy_init, .set_ios_post = rk3568_sdhci_set_ios_post, + .set_enhanced_strobe = rk3568_sdhci_set_enhanced_strobe, }; static const struct udevice_id sdhci_ids[] = {