From patchwork Tue Dec 21 11:20:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1571597 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=FFyHERXA; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JJDYr0YxVz9s0r for ; Tue, 21 Dec 2021 22:21:51 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A2C1C83473; Tue, 21 Dec 2021 12:21:23 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="FFyHERXA"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 643438303F; Tue, 21 Dec 2021 12:20:58 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 42EE6832FC for ; Tue, 21 Dec 2021 12:20:46 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id AC66DB8164B; Tue, 21 Dec 2021 11:20:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 60078C36AF1; Tue, 21 Dec 2021 11:20:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640085644; bh=8WZWXm4fJTlspJXjMS/HIB9Ni4ZrKxS2phRWDkG8GBk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FFyHERXAKlCn7bXlSWT4wQ1HOSaYJ6epRoJ0qN/vUy7NjbdfP0AUYh3oEpcC6epaw SySGSsOtsvhzt3zWMwWmDS1C2Nv5kkFPhXVyeQxTmGaabhr29nk9BPj7tul62EdAfM ZufU+oucTWa82GDJCGXl1MeLKQy1MigR3Y5DTD7Do6PZw8DxTTUUQxPKAR/Rcm3NlK E98bpzuZUq7SxrMzYBg6up65IZ3VVQzKbI0svLx0mHXCgdRHua5CzPBLHdHh6SBFYv EjeeGv8uRchhbohaaAQP8gtRQt2MDsX180PpnTs0pRh7iVvxEm0E/VNNCMrUNfuY6c DPjESTssdj9gw== Received: by pali.im (Postfix) id 19122284D; Tue, 21 Dec 2021 12:20:44 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Stefan Roese , Dirk Eibach , Mario Six , =?utf-8?q?Marek_Beh=C3=BAn?= , Chris Packham Cc: u-boot@lists.denx.de Subject: [PATCH u-boot-marvell 7/9] pci: pci_mvebu: Wait 100ms for Link Up in mvebu_pcie_probe() Date: Tue, 21 Dec 2021 12:20:17 +0100 Message-Id: <20211221112019.15088-8-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211221112019.15088-1-pali@kernel.org> References: <20211221112019.15088-1-pali@kernel.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean After function mvebu_pcie_probe() returns U-Boot DM expects that PCIe link is already up. In followup patches link initialization will be moved from SPL to proper and therefore explicitly link up delay is required. Delay mvebu_pcie_probe() for 100ms to ensure that PCIe link is up after function finish. In the case when no card is connected to the PCIe slot, this will delay probe time by 100ms, which should not be problematic. This change fixes detection and initialization of some QCA98xx cards on the first serdes when configured in x1 mode. Default configuration of the first serdes on A385 is x4 mode, so it looks as if some delay is required when x4 is changed to x1 and card correctly links with A385. Other PCIe serdes ports on A385 are x1-only, and so they don't have this problem. Signed-off-by: Pali Rohár --- drivers/pci/pci_mvebu.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index 504ff501aa2e..b5b0897b2124 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -69,6 +70,9 @@ #define PCIE_DEBUG_CTRL 0x1a60 #define PCIE_DEBUG_SOFT_RESET BIT(20) +#define LINK_WAIT_RETRIES 100 +#define LINK_WAIT_TIMEOUT 1000 + struct mvebu_pcie { struct pci_controller hose; void __iomem *base; @@ -98,6 +102,23 @@ static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie) return !(val & PCIE_STAT_LINK_DOWN); } +static void mvebu_pcie_wait_for_link(struct mvebu_pcie *pcie) +{ + int retries; + + /* check if the link is up or not */ + for (retries = 0; retries < LINK_WAIT_RETRIES; retries++) { + if (mvebu_pcie_link_up(pcie)) { + printf("%s: Link up\n", pcie->name); + return; + } + + udelay(LINK_WAIT_TIMEOUT); + } + + printf("%s: Link down\n", pcie->name); +} + static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno) { u32 stat; @@ -501,6 +522,8 @@ static int mvebu_pcie_probe(struct udevice *dev) pcie->cfgcache[(PCI_PREF_MEMORY_BASE - 0x10) / 4] = PCI_PREF_RANGE_TYPE_64 | (PCI_PREF_RANGE_TYPE_64 << 16); + mvebu_pcie_wait_for_link(pcie); + return 0; }