| Message ID | 20211102231834.1372601-1-ariel.dalessandro@collabora.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Stefano Babic |
| Headers | show |
| Series | imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board | expand |
+Cc Sjoerd On 11/2/21 8:18 PM, Ariel D'Alessandro wrote: > Add support for iMX8MN VAR-SOM-MX8M-NANO board. Enables support for: > > - 1GiB DDR4 RAM > - 16 GiB eMMC > - SD card > - Gigabit ethernet > - USBOTG1 peripheral - fastboot > > Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com> > --- > arch/arm/dts/Makefile | 1 + > arch/arm/dts/imx8mn-var-som-u-boot.dtsi | 220 ++++++++ > arch/arm/dts/imx8mn-var-som.dts | 425 ++++++++++++++ > arch/arm/mach-imx/imx8m/Kconfig | 9 + > board/variscite/imx8mn_var_som/Kconfig | 17 + > board/variscite/imx8mn_var_som/Makefile | 12 + > board/variscite/imx8mn_var_som/ddr4_timing.c | 529 ++++++++++++++++++ > .../variscite/imx8mn_var_som/imx8mn_var_som.c | 35 ++ > .../imx8mn_var_som/imximage-8mn-ddr4.cfg | 12 + > board/variscite/imx8mn_var_som/spl.c | 104 ++++ > configs/imx8mn_var_som_defconfig | 98 ++++ > include/configs/imx8mn_var_som.h | 106 ++++ > 12 files changed, 1568 insertions(+) > create mode 100644 arch/arm/dts/imx8mn-var-som-u-boot.dtsi > create mode 100644 arch/arm/dts/imx8mn-var-som.dts > create mode 100644 board/variscite/imx8mn_var_som/Kconfig > create mode 100644 board/variscite/imx8mn_var_som/Makefile > create mode 100644 board/variscite/imx8mn_var_som/ddr4_timing.c > create mode 100644 board/variscite/imx8mn_var_som/imx8mn_var_som.c > create mode 100644 board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg > create mode 100644 board/variscite/imx8mn_var_som/spl.c > create mode 100644 configs/imx8mn_var_som_defconfig > create mode 100644 include/configs/imx8mn_var_som.h > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index cc34da7bd83..dfa034be80f 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -901,6 +901,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ > imx8mn-ddr4-evk.dtb \ > imx8mq-cm.dtb \ > imx8mn-evk.dtb \ > + imx8mn-var-som.dtb \ > imx8mq-evk.dtb \ > imx8mm-beacon-kit.dtb \ > imx8mn-beacon-kit.dtb \ > diff --git a/arch/arm/dts/imx8mn-var-som-u-boot.dtsi b/arch/arm/dts/imx8mn-var-som-u-boot.dtsi > new file mode 100644 > index 00000000000..73df408bc82 > --- /dev/null > +++ b/arch/arm/dts/imx8mn-var-som-u-boot.dtsi > @@ -0,0 +1,220 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2021 Collabora Ltd. > + */ > + > +/ { > + binman: binman { > + multiple-images; > + }; > + > + wdt-reboot { > + compatible = "wdt-reboot"; > + wdt = <&wdog1>; > + u-boot,dm-spl; > + }; > +}; > + > +&{/soc@0} { > + u-boot,dm-pre-reloc; > + u-boot,dm-spl; > +}; > + > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { > + u-boot,dm-spl; > +}; > + > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { > + u-boot,dm-spl; > +}; > + > +&aips1 { > + u-boot,dm-spl; > + u-boot,dm-pre-reloc; > +}; > + > +&aips3 { > + u-boot,dm-spl; > +}; > + > +&aips4 { > + u-boot,dm-spl; > +}; > + > +&clk { > + u-boot,dm-spl; > + u-boot,dm-pre-reloc; > + /delete-property/ assigned-clocks; > + /delete-property/ assigned-clock-parents; > + /delete-property/ assigned-clock-rates; > +}; > + > +&gpio1 { > + u-boot,dm-spl; > +}; > + > +&gpio2 { > + u-boot,dm-spl; > +}; > + > +&gpio4 { > + u-boot,dm-spl; > +}; > + > +&i2c1 { > + u-boot,dm-spl; > +}; > + > +&iomuxc { > + u-boot,dm-spl; > +}; > + > +&osc_24m { > + u-boot,dm-spl; > + u-boot,dm-pre-reloc; > +}; > + > +&pinctrl_i2c1 { > + u-boot,dm-spl; > +}; > + > +&pinctrl_pmic { > + u-boot,dm-spl; > +}; > + > +&pinctrl_reg_usdhc2_vmmc { > + u-boot,dm-spl; > +}; > + > +&pinctrl_uart4 { > + u-boot,dm-spl; > +}; > + > +&pinctrl_usdhc2 { > + u-boot,dm-spl; > +}; > + > +&pinctrl_usdhc3 { > + u-boot,dm-spl; > +}; > + > +&pinctrl_wdog { > + u-boot,dm-spl; > +}; > + > +&uart4 { > + u-boot,dm-spl; > +}; > + > +&usdhc2 { > + u-boot,dm-spl; > +}; > + > +&usdhc3 { > + u-boot,dm-spl; > +}; > + > +&wdog1 { > + u-boot,dm-spl; > +}; > + > +&binman { > + u-boot-spl-ddr { > + filename = "u-boot-spl-ddr.bin"; > + pad-byte = <0xff>; > + align-size = <4>; > + align = <4>; > + > + u-boot-spl { > + align-end = <4>; > + }; > + > + blob_1: blob-ext@1 { > + filename = "ddr4_imem_1d.bin"; > + size = <0x8000>; > + }; > + > + blob_2: blob-ext@2 { > + filename = "ddr4_dmem_1d.bin"; > + size = <0x4000>; > + }; > + > + blob_3: blob-ext@3 { > + filename = "ddr4_imem_2d.bin"; > + size = <0x8000>; > + }; > + > + blob_4: blob-ext@4 { > + filename = "ddr4_dmem_2d.bin"; > + size = <0x4000>; > + }; > + }; > + > + itb { > + filename = "u-boot.itb"; > + > + fit { > + description = "Configuration to load ATF before U-Boot"; > + #address-cells = <1>; > + fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; > + > + images { > + uboot { > + description = "U-Boot (64-bit)"; > + type = "standalone"; > + arch = "arm64"; > + compression = "none"; > + load = <CONFIG_SYS_TEXT_BASE>; > + > + uboot_blob: blob-ext { > + filename = "u-boot-nodtb.bin"; > + }; > + }; > + > + atf { > + description = "ARM Trusted Firmware"; > + type = "firmware"; > + arch = "arm64"; > + compression = "none"; > + load = <0x960000>; > + entry = <0x960000>; > + > + atf_blob: blob-ext { > + filename = "bl31.bin"; > + }; > + }; > + > + fdt { > + description = "NAME"; > + type = "flat_dt"; > + compression = "none"; > + > + uboot_fdt_blob: blob-ext { > + filename = "u-boot.dtb"; > + }; > + }; > + }; > + > + configurations { > + default = "conf"; > + > + conf { > + description = "NAME"; > + firmware = "uboot"; > + loadables = "atf"; > + fdt = "fdt"; > + }; > + }; > + }; > + }; > + > + flash { > + mkimage { > + args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000"; > + > + blob { > + filename = "u-boot-spl-ddr.bin"; > + }; > + }; > + }; > +}; > diff --git a/arch/arm/dts/imx8mn-var-som.dts b/arch/arm/dts/imx8mn-var-som.dts > new file mode 100644 > index 00000000000..e094d25af8c > --- /dev/null > +++ b/arch/arm/dts/imx8mn-var-som.dts > @@ -0,0 +1,425 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2021 Collabora Ltd. > + */ > + > +/dts-v1/; > + > +#include "imx8mn.dtsi" > + > +/ { > + model = "Variscite VAR-SOM-MX8MN module"; > + compatible = "variscite,var-som-mx8mn", "fsl,imx8mn"; > + > + chosen { > + bootargs = "console=ttymxc3,115200 earlycon=ec_imx6q,0x30a60000,115200"; > + stdout-path = &uart4; > + }; > + > + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { > + compatible = "regulator-fixed"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; > + regulator-name = "VSD_3V3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + > + reg_eth_phy: regulator-eth-phy { > + compatible = "regulator-fixed"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_reg_eth_phy>; > + regulator-name = "eth_phy_pwr"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > +}; > + > +&A53_0 { > + cpu-supply = <&buck2_reg>; > +}; > + > +&A53_1 { > + cpu-supply = <&buck2_reg>; > +}; > + > +&A53_2 { > + cpu-supply = <&buck2_reg>; > +}; > + > +&A53_3 { > + cpu-supply = <&buck2_reg>; > +}; > + > +&fec1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_fec1>; > + phy-mode = "rgmii"; > + phy-handle = <ðphy>; > + phy-supply = <®_eth_phy>; > + phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; > + phy-reset-duration = <10>; > + fsl,magic-packet; > + status = "okay"; > + > + mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + > + ethphy: ethernet-phy@4 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <4>; > + }; > + }; > +}; > + > +&i2c1 { > + clock-frequency = <400000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c1>; > + status = "okay"; > + > + pmic@4b { > + compatible = "rohm,bd71847"; > + reg = <0x4b>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pmic>; > + interrupt-parent = <&gpio2>; > + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; > + rohm,reset-snvs-powered; > + > + regulators { > + buck1_reg: BUCK1 { > + regulator-name = "buck1"; > + regulator-min-microvolt = <700000>; > + regulator-max-microvolt = <1300000>; > + regulator-boot-on; > + regulator-always-on; > + regulator-ramp-delay = <1250>; > + }; > + > + buck2_reg: BUCK2 { > + regulator-name = "buck2"; > + regulator-min-microvolt = <700000>; > + regulator-max-microvolt = <1300000>; > + regulator-boot-on; > + regulator-always-on; > + regulator-ramp-delay = <1250>; > + rohm,dvs-run-voltage = <1000000>; > + rohm,dvs-idle-voltage = <900000>; > + }; > + > + buck3_reg: BUCK3 { > + regulator-name = "buck3"; > + regulator-min-microvolt = <700000>; > + regulator-max-microvolt = <1350000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + buck4_reg: BUCK4 { > + regulator-name = "buck4"; > + regulator-min-microvolt = <2600000>; > + regulator-max-microvolt = <3300000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + buck5_reg: BUCK5 { > + regulator-name = "buck5"; > + regulator-min-microvolt = <1605000>; > + regulator-max-microvolt = <1995000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + buck6_reg: BUCK6 { > + regulator-name = "buck6"; > + regulator-min-microvolt = <800000>; > + regulator-max-microvolt = <1400000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo1_reg: LDO1 { > + regulator-name = "ldo1"; > + regulator-min-microvolt = <1600000>; > + regulator-max-microvolt = <1900000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo2_reg: LDO2 { > + regulator-name = "ldo2"; > + regulator-min-microvolt = <800000>; > + regulator-max-microvolt = <900000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo3_reg: LDO3 { > + regulator-name = "ldo3"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <3300000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo4_reg: LDO4 { > + regulator-name = "ldo4"; > + regulator-min-microvolt = <900000>; > + regulator-max-microvolt = <1800000>; > + regulator-always-on; > + }; > + > + ldo5_reg: LDO5 { > + regulator-name = "ldo5"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-always-on; > + }; > + > + ldo6_reg: LDO6 { > + regulator-name = "ldo6"; > + regulator-min-microvolt = <900000>; > + regulator-max-microvolt = <1800000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + }; > + }; > +}; > + > +/* Console */ > +&uart4 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart4>; > + status = "okay"; > +}; > + > +&usbotg1 { > + dr_mode = "peripheral"; > + status = "okay"; > +}; > + > +/* SD */ > +&usdhc2 { > + assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; > + assigned-clock-rates = <200000000>; > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; > + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; > + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; > + cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; > + bus-width = <4>; > + vmmc-supply = <®_usdhc2_vmmc>; > + status = "okay"; > +}; > + > +/* eMMC */ > +&usdhc3 { > + assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; > + assigned-clock-rates = <400000000>; > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc3>; > + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; > + bus-width = <8>; > + non-removable; > + status = "okay"; > +}; > + > +&wdog1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_wdog>; > + fsl,ext-reset-output; > + status = "okay"; > +}; > + > +&iomuxc { > + pinctrl_fec1: fec1grp { > + fsl,pins = < > + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 > + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 > + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f > + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f > + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f > + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f > + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 > + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 > + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 > + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 > + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f > + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 > + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 > + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f > + MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 > + >; > + }; > + > + pinctrl_i2c1: i2c1grp { > + fsl,pins = < > + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 > + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 > + >; > + }; > + > + pinctrl_pmic: pmicirqgrp { > + fsl,pins = < > + MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141 > + >; > + }; > + > + pinctrl_reg_eth_phy: regethphygrp { > + fsl,pins = < > + MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 > + >; > + }; > + > + > + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { > + fsl,pins = < > + MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41 > + >; > + }; > + > + pinctrl_uart4: uart4grp { > + fsl,pins = < > + MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 > + MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 > + >; > + }; > + > + pinctrl_usdhc1: usdhc1grp { > + fsl,pins = < > + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 > + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 > + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 > + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 > + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 > + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 > + >; > + }; > + > + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { > + fsl,pins = < > + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 > + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 > + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 > + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 > + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 > + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 > + >; > + }; > + > + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { > + fsl,pins = < > + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 > + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 > + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 > + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 > + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 > + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 > + >; > + }; > + > + pinctrl_usdhc2_gpio: usdhc2gpiogrp { > + fsl,pins = < > + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 > + >; > + }; > + > + pinctrl_usdhc2: usdhc2grp { > + fsl,pins = < > + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 > + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 > + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 > + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 > + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 > + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 > + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 > + >; > + }; > + > + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { > + fsl,pins = < > + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 > + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 > + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 > + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 > + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 > + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 > + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 > + >; > + }; > + > + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { > + fsl,pins = < > + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 > + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 > + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 > + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 > + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 > + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 > + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 > + >; > + }; > + > + pinctrl_usdhc3: usdhc3grp { > + fsl,pins = < > + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 > + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 > + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 > + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 > + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 > + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 > + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 > + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 > + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 > + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 > + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 > + >; > + }; > + > + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { > + fsl,pins = < > + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 > + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 > + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 > + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 > + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 > + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 > + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 > + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 > + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 > + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 > + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 > + >; > + }; > + > + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { > + fsl,pins = < > + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 > + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 > + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 > + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 > + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 > + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 > + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 > + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 > + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 > + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 > + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 > + >; > + }; > + > + pinctrl_wdog: wdoggrp { > + fsl,pins = < > + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 > + >; > + }; > +}; > diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig > index 276b8bd9742..82a5ab8ad00 100644 > --- a/arch/arm/mach-imx/imx8m/Kconfig > +++ b/arch/arm/mach-imx/imx8m/Kconfig > @@ -108,6 +108,14 @@ config TARGET_PICO_IMX8MQ > select IMX8MQ > select IMX8M_LPDDR4 > > +config TARGET_IMX8MN_VAR_SOM > + bool "imx8mn_var_som" > + select BINMAN > + select IMX8MN > + select SUPPORT_SPL > + select IMX8M_DDR4 > + select IMX8M_BOARD_INIT_DRAM > + > config TARGET_VERDIN_IMX8MM > bool "Support Toradex Verdin iMX8M Mini module" > select BINMAN > @@ -171,6 +179,7 @@ source "board/phytec/phycore_imx8mm/Kconfig" > source "board/phytec/phycore_imx8mp/Kconfig" > source "board/ronetix/imx8mq-cm/Kconfig" > source "board/technexion/pico-imx8mq/Kconfig" > +source "board/variscite/imx8mn_var_som/Kconfig" > source "board/toradex/verdin-imx8mm/Kconfig" > > endif > diff --git a/board/variscite/imx8mn_var_som/Kconfig b/board/variscite/imx8mn_var_som/Kconfig > new file mode 100644 > index 00000000000..cfe6fc8c2c7 > --- /dev/null > +++ b/board/variscite/imx8mn_var_som/Kconfig > @@ -0,0 +1,17 @@ > +if TARGET_IMX8MN_VAR_SOM > + > +config SYS_BOARD > + default "imx8mn_var_som" > + > +config SYS_VENDOR > + default "variscite" > + > +config SYS_CONFIG_NAME > + default "imx8mn_var_som" > + > +config IMX_CONFIG > + default "board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg" > + > +source "board/freescale/common/Kconfig" > + > +endif > diff --git a/board/variscite/imx8mn_var_som/Makefile b/board/variscite/imx8mn_var_som/Makefile > new file mode 100644 > index 00000000000..a8b6a343ffc > --- /dev/null > +++ b/board/variscite/imx8mn_var_som/Makefile > @@ -0,0 +1,12 @@ > +# > +# Copyright 2021 Collabora Ltd. > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +obj-y += imx8mn_var_som.o > + > +ifdef CONFIG_SPL_BUILD > +obj-y += spl.o > +obj-y += ddr4_timing.o > +endif > diff --git a/board/variscite/imx8mn_var_som/ddr4_timing.c b/board/variscite/imx8mn_var_som/ddr4_timing.c > new file mode 100644 > index 00000000000..6d3d1805c89 > --- /dev/null > +++ b/board/variscite/imx8mn_var_som/ddr4_timing.c > @@ -0,0 +1,529 @@ > +/* > + * Copyright 2019 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + * > + * Generated code from MX8M_DDR_tool > + * Align with uboot version: > + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga > + */ > + > +#include <linux/kernel.h> > +#include <asm/arch/ddr.h> > + > +static struct dram_cfg_param ddr_ddrc_cfg[] = { > + /** Initialize DDRC registers **/ > + { 0x3d400000, 0x81040010 }, > + { 0x3d400030, 0x20 }, > + { 0x3d400034, 0x221306 }, > + { 0x3d400050, 0x210070 }, > + { 0x3d400054, 0x10008 }, > + { 0x3d400060, 0x0 }, > + { 0x3d400064, 0x9200d2 }, > + { 0x3d4000c0, 0x0 }, > + { 0x3d4000c4, 0x1000 }, > + { 0x3d4000d0, 0xc0030126 }, > + { 0x3d4000d4, 0x770000 }, > + { 0x3d4000dc, 0x8340105 }, > + { 0x3d4000e0, 0x180200 }, > + { 0x3d4000e4, 0x110000 }, > + { 0x3d4000e8, 0x2000600 }, > + { 0x3d4000ec, 0x810 }, > + { 0x3d4000f0, 0x20 }, > + { 0x3d4000f4, 0xec7 }, > + { 0x3d400100, 0x11122914 }, > + { 0x3d400104, 0x4051c }, > + { 0x3d400108, 0x608050d }, > + { 0x3d40010c, 0x400c }, > + { 0x3d400110, 0x8030409 }, > + { 0x3d400114, 0x6060403 }, > + { 0x3d40011c, 0x606 }, > + { 0x3d400120, 0x5050d08 }, > + { 0x3d400124, 0x2040a }, > + { 0x3d40012c, 0x1409010e }, > + { 0x3d400130, 0x8 }, > + { 0x3d40013c, 0x0 }, > + { 0x3d400180, 0x1000040 }, > + { 0x3d400184, 0x493e }, > + { 0x3d400190, 0x38b8207 }, > + { 0x3d400194, 0x2020303 }, > + { 0x3d400198, 0x7f04011 }, > + { 0x3d40019c, 0xb0 }, > + { 0x3d4001a0, 0xe0400018 }, > + { 0x3d4001a4, 0x48005a }, > + { 0x3d4001a8, 0x80000000 }, > + { 0x3d4001b0, 0x1 }, > + { 0x3d4001b4, 0xb07 }, > + { 0x3d4001b8, 0x4 }, > + { 0x3d4001c0, 0x1 }, > + { 0x3d4001c4, 0x0 }, > + { 0x3d400200, 0x3f1f }, > + { 0x3d400204, 0x3f0909 }, > + { 0x3d400208, 0x700 }, > + { 0x3d40020c, 0x0 }, > + { 0x3d400210, 0x1f1f }, > + { 0x3d400214, 0x7070707 }, > + { 0x3d400218, 0x7070707 }, > + { 0x3d40021c, 0xf0f }, > + { 0x3d400220, 0x3f01 }, > + { 0x3d400240, 0x6000610 }, > + { 0x3d400244, 0x1323 }, > + { 0x3d400400, 0x100 }, > + { 0x3d400250, 0x317d1a07 }, > + { 0x3d400254, 0xf }, > + { 0x3d40025c, 0x2a001b76 }, > + { 0x3d400264, 0x7300b473 }, > + { 0x3d40026c, 0x30000e06 }, > + { 0x3d400300, 0x14 }, > + { 0x3d40036c, 0x10 }, > + { 0x3d400404, 0x13193 }, > + { 0x3d400408, 0x6096 }, > + { 0x3d400490, 0x1 }, > + { 0x3d400494, 0x2000c00 }, > + { 0x3d400498, 0x3c00db }, > + { 0x3d40049c, 0x100009 }, > + { 0x3d4004a0, 0x2 }, > + { 0x3d402050, 0x210070 }, > + { 0x3d402064, 0x40005e }, > + { 0x3d4020dc, 0x40105 }, > + { 0x3d4020e0, 0x0 }, > + { 0x3d4020e8, 0x2000600 }, > + { 0x3d4020ec, 0x10 }, > + { 0x3d402100, 0xb081209 }, > + { 0x3d402104, 0x2020d }, > + { 0x3d402108, 0x5050309 }, > + { 0x3d40210c, 0x400c }, > + { 0x3d402110, 0x5030206 }, > + { 0x3d402114, 0x3030202 }, > + { 0x3d40211c, 0x303 }, > + { 0x3d402120, 0x3030d04 }, > + { 0x3d402124, 0x20208 }, > + { 0x3d40212c, 0x1005010e }, > + { 0x3d402130, 0x8 }, > + { 0x3d40213c, 0x0 }, > + { 0x3d402180, 0x1000040 }, > + { 0x3d402190, 0x3858204 }, > + { 0x3d402194, 0x2020303 }, > + { 0x3d4021b4, 0x504 }, > + { 0x3d4021b8, 0x4 }, > + { 0x3d402240, 0x6000604 }, > + { 0x3d4020f4, 0xec7 }, > +}; > + > +/* PHY Initialize Configuration */ > +static struct dram_cfg_param ddr_ddrphy_cfg[] = { > + { 0x1005f, 0x2fd }, > + { 0x1015f, 0x2fd }, > + { 0x1105f, 0x2fd }, > + { 0x1115f, 0x2fd }, > + { 0x11005f, 0x2fd }, > + { 0x11015f, 0x2fd }, > + { 0x11105f, 0x2fd }, > + { 0x11115f, 0x2fd }, > + { 0x55, 0x355 }, > + { 0x1055, 0x355 }, > + { 0x2055, 0x355 }, > + { 0x3055, 0x355 }, > + { 0x4055, 0x55 }, > + { 0x5055, 0x55 }, > + { 0x6055, 0x355 }, > + { 0x7055, 0x355 }, > + { 0x8055, 0x355 }, > + { 0x9055, 0x355 }, > + { 0x200c5, 0xa }, > + { 0x1200c5, 0x6 }, > + { 0x2002e, 0x2 }, > + { 0x12002e, 0x1 }, > + { 0x20024, 0x8 }, > + { 0x2003a, 0x2 }, > + { 0x120024, 0x8 }, > + { 0x2003a, 0x2 }, > + { 0x20056, 0x6 }, > + { 0x120056, 0xa }, > + { 0x1004d, 0x1a }, > + { 0x1014d, 0x1a }, > + { 0x1104d, 0x1a }, > + { 0x1114d, 0x1a }, > + { 0x11004d, 0x1a }, > + { 0x11014d, 0x1a }, > + { 0x11104d, 0x1a }, > + { 0x11114d, 0x1a }, > + { 0x10049, 0xe38 }, > + { 0x10149, 0xe38 }, > + { 0x11049, 0xe38 }, > + { 0x11149, 0xe38 }, > + { 0x110049, 0xe38 }, > + { 0x110149, 0xe38 }, > + { 0x111049, 0xe38 }, > + { 0x111149, 0xe38 }, > + { 0x43, 0x63 }, > + { 0x1043, 0x63 }, > + { 0x2043, 0x63 }, > + { 0x3043, 0x63 }, > + { 0x4043, 0x63 }, > + { 0x5043, 0x63 }, > + { 0x6043, 0x63 }, > + { 0x7043, 0x63 }, > + { 0x8043, 0x63 }, > + { 0x9043, 0x63 }, > + { 0x20018, 0x1 }, > + { 0x20075, 0x2 }, > + { 0x20050, 0x0 }, > + { 0x20008, 0x258 }, > + { 0x120008, 0x10a }, > + { 0x20088, 0x9 }, > + { 0x200b2, 0x268 }, > + { 0x10043, 0x5b1 }, > + { 0x10143, 0x5b1 }, > + { 0x11043, 0x5b1 }, > + { 0x11143, 0x5b1 }, > + { 0x1200b2, 0x268 }, > + { 0x110043, 0x5b1 }, > + { 0x110143, 0x5b1 }, > + { 0x111043, 0x5b1 }, > + { 0x111143, 0x5b1 }, > + { 0x200fa, 0x1 }, > + { 0x1200fa, 0x1 }, > + { 0x20019, 0x5 }, > + { 0x120019, 0x5 }, > + { 0x200f0, 0x5555 }, > + { 0x200f1, 0x5555 }, > + { 0x200f2, 0x5555 }, > + { 0x200f3, 0x5555 }, > + { 0x200f4, 0x5555 }, > + { 0x200f5, 0x5555 }, > + { 0x200f6, 0x5555 }, > + { 0x200f7, 0xf000 }, > + { 0x20025, 0x0 }, > + { 0x2002d, 0x0 }, > + { 0x12002d, 0x0 }, > + { 0x2005b, 0x7529 }, > + { 0x2005c, 0x0 }, > + { 0x200c7, 0x21 }, > + { 0x200ca, 0x24 }, > + { 0x200cc, 0x1f7 }, > + { 0x1200c7, 0x21 }, > + { 0x1200ca, 0x24 }, > + { 0x1200cc, 0x1f7 }, > + { 0x2007d, 0x212 }, > + { 0x12007d, 0x212 }, > + { 0x2007c, 0x61 }, > + { 0x12007c, 0x61 }, > + { 0x1004a, 0x500 }, > + { 0x1104a, 0x500 }, > + { 0x2002c, 0x0 }, > +}; > + > +/* P0 message block parameter for training firmware */ > +static struct dram_cfg_param ddr_fsp0_cfg[] = { > + { 0xd0000, 0x0 }, > + { 0x54003, 0x960 }, > + { 0x54004, 0x2 }, > + { 0x54005, 0x2830 }, > + { 0x54006, 0x25e }, > + { 0x54007, 0x1000 }, > + { 0x54008, 0x101 }, > + { 0x5400b, 0x31f }, > + { 0x5400c, 0xc8 }, > + { 0x5400d, 0x100 }, > + { 0x54012, 0x1 }, > + { 0x5402f, 0x834 }, > + { 0x54030, 0x105 }, > + { 0x54031, 0x18 }, > + { 0x54032, 0x200 }, > + { 0x54033, 0x200 }, > + { 0x54034, 0x600 }, > + { 0x54035, 0x810 }, > + { 0x54036, 0x101 }, > + { 0x5403f, 0x1221 }, > + { 0x541fc, 0x100 }, > + { 0xd0000, 0x1 }, > +}; > + > +/* P1 message block parameter for training firmware */ > +static struct dram_cfg_param ddr_fsp1_cfg[] = { > + { 0xd0000, 0x0 }, > + { 0x54002, 0x1 }, > + { 0x54003, 0x42a }, > + { 0x54004, 0x2 }, > + { 0x54005, 0x2830 }, > + { 0x54006, 0x25e }, > + { 0x54007, 0x1000 }, > + { 0x54008, 0x101 }, > + { 0x5400b, 0x21f }, > + { 0x5400c, 0xc8 }, > + { 0x5400d, 0x100 }, > + { 0x54012, 0x1 }, > + { 0x5402f, 0x4 }, > + { 0x54030, 0x105 }, > + { 0x54033, 0x200 }, > + { 0x54034, 0x600 }, > + { 0x54035, 0x10 }, > + { 0x54036, 0x101 }, > + { 0x5403f, 0x1221 }, > + { 0x541fc, 0x100 }, > + { 0xd0000, 0x1 }, > +}; > + > +/* P0 2D message block parameter for training firmware */ > +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { > + { 0xd0000, 0x0 }, > + { 0x54003, 0x960 }, > + { 0x54004, 0x2 }, > + { 0x54005, 0x2830 }, > + { 0x54006, 0x25e }, > + { 0x54007, 0x1000 }, > + { 0x54008, 0x101 }, > + { 0x5400b, 0x61 }, > + { 0x5400c, 0xc8 }, > + { 0x5400d, 0x100 }, > + { 0x5400e, 0x1f7f }, > + { 0x54012, 0x1 }, > + { 0x5402f, 0x834 }, > + { 0x54030, 0x105 }, > + { 0x54031, 0x18 }, > + { 0x54032, 0x200 }, > + { 0x54033, 0x200 }, > + { 0x54034, 0x600 }, > + { 0x54035, 0x810 }, > + { 0x54036, 0x101 }, > + { 0x5403f, 0x1221 }, > + { 0x541fc, 0x100 }, > + { 0xd0000, 0x1 }, > +}; > + > +/* DRAM PHY init engine image */ > +static struct dram_cfg_param ddr_phy_pie[] = { > + { 0xd0000, 0x0 }, > + { 0x90000, 0x10 }, > + { 0x90001, 0x400 }, > + { 0x90002, 0x10e }, > + { 0x90003, 0x0 }, > + { 0x90004, 0x0 }, > + { 0x90005, 0x8 }, > + { 0x90029, 0xb }, > + { 0x9002a, 0x480 }, > + { 0x9002b, 0x109 }, > + { 0x9002c, 0x8 }, > + { 0x9002d, 0x448 }, > + { 0x9002e, 0x139 }, > + { 0x9002f, 0x8 }, > + { 0x90030, 0x478 }, > + { 0x90031, 0x109 }, > + { 0x90032, 0x2 }, > + { 0x90033, 0x10 }, > + { 0x90034, 0x139 }, > + { 0x90035, 0xb }, > + { 0x90036, 0x7c0 }, > + { 0x90037, 0x139 }, > + { 0x90038, 0x44 }, > + { 0x90039, 0x633 }, > + { 0x9003a, 0x159 }, > + { 0x9003b, 0x14f }, > + { 0x9003c, 0x630 }, > + { 0x9003d, 0x159 }, > + { 0x9003e, 0x47 }, > + { 0x9003f, 0x633 }, > + { 0x90040, 0x149 }, > + { 0x90041, 0x4f }, > + { 0x90042, 0x633 }, > + { 0x90043, 0x179 }, > + { 0x90044, 0x8 }, > + { 0x90045, 0xe0 }, > + { 0x90046, 0x109 }, > + { 0x90047, 0x0 }, > + { 0x90048, 0x7c8 }, > + { 0x90049, 0x109 }, > + { 0x9004a, 0x0 }, > + { 0x9004b, 0x1 }, > + { 0x9004c, 0x8 }, > + { 0x9004d, 0x0 }, > + { 0x9004e, 0x45a }, > + { 0x9004f, 0x9 }, > + { 0x90050, 0x0 }, > + { 0x90051, 0x448 }, > + { 0x90052, 0x109 }, > + { 0x90053, 0x40 }, > + { 0x90054, 0x633 }, > + { 0x90055, 0x179 }, > + { 0x90056, 0x1 }, > + { 0x90057, 0x618 }, > + { 0x90058, 0x109 }, > + { 0x90059, 0x40c0 }, > + { 0x9005a, 0x633 }, > + { 0x9005b, 0x149 }, > + { 0x9005c, 0x8 }, > + { 0x9005d, 0x4 }, > + { 0x9005e, 0x48 }, > + { 0x9005f, 0x4040 }, > + { 0x90060, 0x633 }, > + { 0x90061, 0x149 }, > + { 0x90062, 0x0 }, > + { 0x90063, 0x4 }, > + { 0x90064, 0x48 }, > + { 0x90065, 0x40 }, > + { 0x90066, 0x633 }, > + { 0x90067, 0x149 }, > + { 0x90068, 0x10 }, > + { 0x90069, 0x4 }, > + { 0x9006a, 0x18 }, > + { 0x9006b, 0x0 }, > + { 0x9006c, 0x4 }, > + { 0x9006d, 0x78 }, > + { 0x9006e, 0x549 }, > + { 0x9006f, 0x633 }, > + { 0x90070, 0x159 }, > + { 0x90071, 0xd49 }, > + { 0x90072, 0x633 }, > + { 0x90073, 0x159 }, > + { 0x90074, 0x94a }, > + { 0x90075, 0x633 }, > + { 0x90076, 0x159 }, > + { 0x90077, 0x441 }, > + { 0x90078, 0x633 }, > + { 0x90079, 0x149 }, > + { 0x9007a, 0x42 }, > + { 0x9007b, 0x633 }, > + { 0x9007c, 0x149 }, > + { 0x9007d, 0x1 }, > + { 0x9007e, 0x633 }, > + { 0x9007f, 0x149 }, > + { 0x90080, 0x0 }, > + { 0x90081, 0xe0 }, > + { 0x90082, 0x109 }, > + { 0x90083, 0xa }, > + { 0x90084, 0x10 }, > + { 0x90085, 0x109 }, > + { 0x90086, 0x9 }, > + { 0x90087, 0x3c0 }, > + { 0x90088, 0x149 }, > + { 0x90089, 0x9 }, > + { 0x9008a, 0x3c0 }, > + { 0x9008b, 0x159 }, > + { 0x9008c, 0x18 }, > + { 0x9008d, 0x10 }, > + { 0x9008e, 0x109 }, > + { 0x9008f, 0x0 }, > + { 0x90090, 0x3c0 }, > + { 0x90091, 0x109 }, > + { 0x90092, 0x18 }, > + { 0x90093, 0x4 }, > + { 0x90094, 0x48 }, > + { 0x90095, 0x18 }, > + { 0x90096, 0x4 }, > + { 0x90097, 0x58 }, > + { 0x90098, 0xb }, > + { 0x90099, 0x10 }, > + { 0x9009a, 0x109 }, > + { 0x9009b, 0x1 }, > + { 0x9009c, 0x10 }, > + { 0x9009d, 0x109 }, > + { 0x9009e, 0x5 }, > + { 0x9009f, 0x7c0 }, > + { 0x900a0, 0x109 }, > + { 0x900a1, 0x0 }, > + { 0x900a2, 0x8140 }, > + { 0x900a3, 0x10c }, > + { 0x900a4, 0x10 }, > + { 0x900a5, 0x8138 }, > + { 0x900a6, 0x10c }, > + { 0x900a7, 0x8 }, > + { 0x900a8, 0x7c8 }, > + { 0x900a9, 0x101 }, > + { 0x900aa, 0x8 }, > + { 0x900ab, 0x448 }, > + { 0x900ac, 0x109 }, > + { 0x900ad, 0xf }, > + { 0x900ae, 0x7c0 }, > + { 0x900af, 0x109 }, > + { 0x900b0, 0x47 }, > + { 0x900b1, 0x630 }, > + { 0x900b2, 0x109 }, > + { 0x900b3, 0x8 }, > + { 0x900b4, 0x618 }, > + { 0x900b5, 0x109 }, > + { 0x900b6, 0x8 }, > + { 0x900b7, 0xe0 }, > + { 0x900b8, 0x109 }, > + { 0x900b9, 0x0 }, > + { 0x900ba, 0x7c8 }, > + { 0x900bb, 0x109 }, > + { 0x900bc, 0x8 }, > + { 0x900bd, 0x8140 }, > + { 0x900be, 0x10c }, > + { 0x900bf, 0x0 }, > + { 0x900c0, 0x1 }, > + { 0x900c1, 0x8 }, > + { 0x900c2, 0x8 }, > + { 0x900c3, 0x4 }, > + { 0x900c4, 0x8 }, > + { 0x900c5, 0x8 }, > + { 0x900c6, 0x7c8 }, > + { 0x900c7, 0x101 }, > + { 0x90006, 0x0 }, > + { 0x90007, 0x0 }, > + { 0x90008, 0x8 }, > + { 0x90009, 0x0 }, > + { 0x9000a, 0x0 }, > + { 0x9000b, 0x0 }, > + { 0xd00e7, 0x400 }, > + { 0x90017, 0x0 }, > + { 0x90026, 0x2b }, > + { 0x2000b, 0x4b }, > + { 0x2000c, 0x96 }, > + { 0x2000d, 0x5dc }, > + { 0x2000e, 0x2c }, > + { 0x12000b, 0x21 }, > + { 0x12000c, 0x42 }, > + { 0x12000d, 0x29a }, > + { 0x12000e, 0x21 }, > + { 0x9000c, 0x0 }, > + { 0x9000d, 0x173 }, > + { 0x9000e, 0x60 }, > + { 0x9000f, 0x6110 }, > + { 0x90010, 0x2152 }, > + { 0x90011, 0xdfbd }, > + { 0x90012, 0xffff }, > + { 0x90013, 0x6152 }, > + { 0x20089, 0x1 }, > + { 0x20088, 0x19 }, > + { 0xc0080, 0x0 }, > + { 0xd0000, 0x1 }, > +}; > + > +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { > + { > + /* P0 2400mts 1D */ > + .drate = 2400, > + .fw_type = FW_1D_IMAGE, > + .fsp_cfg = ddr_fsp0_cfg, > + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), > + }, > + { > + /* P1 1066mts 1D */ > + .drate = 1066, > + .fw_type = FW_1D_IMAGE, > + .fsp_cfg = ddr_fsp1_cfg, > + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), > + }, > + { > + /* P0 2400mts 2D */ > + .drate = 2400, > + .fw_type = FW_2D_IMAGE, > + .fsp_cfg = ddr_fsp0_2d_cfg, > + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), > + }, > +}; > + > +/* ddr timing config params */ > +struct dram_timing_info dram_timing = { > + .ddrc_cfg = ddr_ddrc_cfg, > + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), > + .ddrphy_cfg = ddr_ddrphy_cfg, > + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), > + .fsp_msg = ddr_dram_fsp_msg, > + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), > + .ddrphy_pie = ddr_phy_pie, > + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), > + .fsp_table = { 2400, 1066, }, > +}; > diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c b/board/variscite/imx8mn_var_som/imx8mn_var_som.c > new file mode 100644 > index 00000000000..1d2f8a40590 > --- /dev/null > +++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c > @@ -0,0 +1,35 @@ > +/* > + * Copyright 2021 Collabora Ltd. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <env.h> > +#include <asm/io.h> > + > +#if IS_ENABLED(CONFIG_FEC_MXC) > +static int setup_fec(void) > +{ > + struct iomuxc_gpr_base_regs *gpr = > + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; > + > + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ > + clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); > + > + return 0; > +} > +#endif > + > +int board_init(void) > +{ > + if (IS_ENABLED(CONFIG_FEC_MXC)) > + setup_fec(); > + > + return 0; > +} > + > +int board_mmc_get_env_dev(int devno) > +{ > + return devno; > +} > diff --git a/board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg b/board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg > new file mode 100644 > index 00000000000..a24856eb631 > --- /dev/null > +++ b/board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg > @@ -0,0 +1,12 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright 2021 Collabora Ltd. > + */ > + > +#define __ASSEMBLY__ > + > +FIT > +ROM_VERSION v2 > +BOOT_FROM sd > +LOADER u-boot-spl-ddr.bin 0x912000 > +SECOND_LOADER u-boot.itb 0x40200000 0x60000 > diff --git a/board/variscite/imx8mn_var_som/spl.c b/board/variscite/imx8mn_var_som/spl.c > new file mode 100644 > index 00000000000..f7e17f65127 > --- /dev/null > +++ b/board/variscite/imx8mn_var_som/spl.c > @@ -0,0 +1,104 @@ > +/* > + * Copyright 2021 Collabora Ltd. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <hang.h> > +#include <init.h> > +#include <spl.h> > +#include <asm/arch/clock.h> > +#include <asm/arch/ddr.h> > +#include <asm/arch/imx8mn_pins.h> > +#include <asm/arch/sys_proto.h> > +#include <asm/mach-imx/boot_mode.h> > +#include <asm/mach-imx/gpio.h> > + > +#include <dm/device.h> > +#include <dm/uclass.h> > + > +int spl_board_boot_device(enum boot_device boot_dev_spl) > +{ > + return BOOT_DEVICE_BOOTROM; > +} > + > +void spl_dram_init(void) > +{ > + ddr_init(&dram_timing); > +} > + > +void spl_board_init(void) > +{ > + struct udevice *dev; > + int ret; > + > + debug("Normal Boot\n"); > + > + ret = uclass_get_device_by_name(UCLASS_CLK, > + "clock-controller@30380000", > + &dev); > + if (ret < 0) > + puts("Failed to find clock node. Check device tree\n"); > +} > + > +#ifdef CONFIG_SPL_LOAD_FIT > +int board_fit_config_name_match(const char *name) > +{ > + /* Just empty function now - can't decide what to choose */ > + debug("%s: %s\n", __func__, name); > + > + return 0; > +} > +#endif > + > +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) > +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) > + > +static iomux_v3_cfg_t const uart_pads[] = { > + IMX8MN_PAD_UART4_RXD__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), > + IMX8MN_PAD_UART4_TXD__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), > +}; > + > +static iomux_v3_cfg_t const wdog_pads[] = { > + IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), > +}; > + > +int board_early_init_f(void) > +{ > + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; > + > + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); > + set_wdog_reset(wdog); > + > + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); > + init_uart_clk(3); > + > + return 0; > +} > + > +void board_init_f(ulong dummy) > +{ > + int ret; > + > + /* Clear the BSS. */ > + memset(__bss_start, 0, __bss_end - __bss_start); > + > + arch_cpu_init(); > + > + board_early_init_f(); > + > + timer_init(); > + > + preloader_console_init(); > + > + ret = spl_init(); > + if (ret) { > + debug("spl_init() failed: %d\n", ret); > + hang(); > + } > + > + /* DDR initialization */ > + spl_dram_init(); > + > + board_init_r(NULL, 0); > +} > diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig > new file mode 100644 > index 00000000000..41d317fd5b0 > --- /dev/null > +++ b/configs/imx8mn_var_som_defconfig > @@ -0,0 +1,98 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_IMX8M=y > +CONFIG_SYS_TEXT_BASE=0x40200000 > +CONFIG_SYS_MALLOC_LEN=0x2000000 > +CONFIG_SYS_MALLOC_F_LEN=0x10000 > +CONFIG_SPL_GPIO=y > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > +CONFIG_NR_DRAM_BANKS=1 > +CONFIG_ENV_SIZE=0x2000 > +CONFIG_ENV_OFFSET=0xFFFFDE00 > +CONFIG_DM_GPIO=y > +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-var-som" > +CONFIG_SPL_TEXT_BASE=0x912000 > +CONFIG_TARGET_IMX8MN_VAR_SOM=y > +CONFIG_SPL_MMC=y > +CONFIG_SPL_SERIAL=y > +CONFIG_SPL_DRIVERS_MISC=y > +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 > +CONFIG_SPL=y > +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 > +CONFIG_DISTRO_DEFAULTS=y > +CONFIG_SYS_LOAD_ADDR=0x40480000 > +CONFIG_FIT=y > +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 > +CONFIG_SPL_LOAD_FIT=y > +# CONFIG_USE_SPL_FIT_GENERATOR is not set > +CONFIG_OF_SYSTEM_SETUP=y > +CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-var-som-symphony.dtb" > +CONFIG_ARCH_MISC_INIT=y > +CONFIG_SPL_BOARD_INIT=y > +CONFIG_SPL_BOOTROM_SUPPORT=y > +CONFIG_SPL_SEPARATE_BSS=y > +CONFIG_SPL_I2C=y > +CONFIG_SPL_POWER=y > +CONFIG_SPL_WATCHDOG=y > +CONFIG_SYS_PROMPT="> " > +CONFIG_CMD_FUSE=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_USB=y > +CONFIG_CMD_USB_MASS_STORAGE=y > +CONFIG_OF_CONTROL=y > +CONFIG_SPL_OF_CONTROL=y > +CONFIG_ENV_IS_IN_MMC=y > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y > +CONFIG_SYS_MMC_ENV_DEV=2 > +CONFIG_SYS_MMC_ENV_PART=1 > +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y > +CONFIG_NET_RANDOM_ETHADDR=y > +CONFIG_SPL_DM=y > +CONFIG_REGMAP=y > +CONFIG_SYSCON=y > +CONFIG_SPL_CLK_COMPOSITE_CCF=y > +CONFIG_CLK_COMPOSITE_CCF=y > +CONFIG_SPL_CLK_IMX8MN=y > +CONFIG_CLK_IMX8MN=y > +CONFIG_USB_FUNCTION_FASTBOOT=y > +CONFIG_FASTBOOT_BUF_ADDR=0x40480000 > +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 > +CONFIG_FASTBOOT_FLASH=y > +CONFIG_FASTBOOT_UUU_SUPPORT=y > +CONFIG_FASTBOOT_FLASH_MMC_DEV=2 > +CONFIG_MXC_GPIO=y > +CONFIG_DM_I2C=y > +CONFIG_SUPPORT_EMMC_BOOT=y > +CONFIG_MMC_IO_VOLTAGE=y > +CONFIG_MMC_UHS_SUPPORT=y > +CONFIG_MMC_HS400_ES_SUPPORT=y > +CONFIG_MMC_HS400_SUPPORT=y > +CONFIG_FSL_ESDHC_IMX=y > +CONFIG_PHYLIB=y > +CONFIG_PHY_ATHEROS=y > +CONFIG_DM_ETH=y > +CONFIG_PHY_GIGE=y > +CONFIG_FEC_MXC=y > +CONFIG_MII=y > +CONFIG_PINCTRL=y > +CONFIG_SPL_PINCTRL=y > +CONFIG_PINCTRL_IMX8M=y > +CONFIG_DM_PMIC=y > +CONFIG_DM_PMIC_BD71837=y > +CONFIG_SPL_DM_PMIC_BD71837=y > +CONFIG_DM_REGULATOR=y > +CONFIG_DM_REGULATOR_FIXED=y > +CONFIG_DM_REGULATOR_GPIO=y > +CONFIG_MXC_UART=y > +CONFIG_SYSRESET=y > +CONFIG_SYSRESET_PSCI=y > +CONFIG_SYSRESET_WATCHDOG=y > +CONFIG_USB=y > +CONFIG_USB_EHCI_HCD=y > +CONFIG_USB_GADGET=y > +CONFIG_USB_GADGET_MANUFACTURER="FSL" > +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 > +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 > +CONFIG_CI_UDC=y > +CONFIG_IMX_WATCHDOG=y > +CONFIG_OF_LIBFDT_OVERLAY=y > diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h > new file mode 100644 > index 00000000000..0ba1af135ff > --- /dev/null > +++ b/include/configs/imx8mn_var_som.h > @@ -0,0 +1,106 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright 2021 Collabora Ltd. > + */ > + > +#ifndef __IMX8MN_VAR_SOM_H > +#define __IMX8MN_VAR_SOM_H > + > +#include <linux/sizes.h> > +#include <linux/stringify.h> > +#include <asm/arch/imx-regs.h> > + > +#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) > + > +#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K) > +#define CONFIG_SYS_MONITOR_LEN SZ_512K > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 > +#define CONFIG_SYS_UBOOT_BASE \ > + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) > + > +#ifdef CONFIG_SPL_BUILD > + > +#define CONFIG_SPL_STACK 0x980000 > +#define CONFIG_SPL_BSS_START_ADDR 0x950000 > +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ > +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 > +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ > + > +/* For RAW image gives a error info not panic */ > +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE > + > +#endif /* CONFIG_SPL_BUILD */ > + > +#ifndef CONFIG_SPL_BUILD > + > +#define BOOT_TARGET_DEVICES(func) \ > + func(MMC, mmc, 1) \ > + func(MMC, mmc, 2) \ > + func(MMC, mmc, 0) \ > + func(PXE, pxe, na) \ > + func(DHCP, dhcp, na) \ > + > +#include <config_distro_bootcmd.h> > + > +#endif /* !CONFIG_SPL_BUILD */ > + > +/* ENET */ > +#if defined(CONFIG_FEC_MXC) > +#define CONFIG_ETHPRIME "FEC" > +#define CONFIG_FEC_XCV_TYPE RGMII > +#endif /* CONFIG_FEC_MXC */ > + > +#define MEM_LAYOUT_ENV_SETTINGS \ > + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ > + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ > + "ramdisk_addr_r=0x43800000\0" \ > + "fdt_addr_r=0x43000000\0" \ > + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ > + "fastboot_partition_alias_all=" \ > + __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) ".0:0\0" \ > + "fastboot_partition_alias_bootloader=" \ > + __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) ".1:0\0" \ > + "emmc_dev=" __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) "\0" \ > + "emmc_ack=1\0" \ > + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ > + > +/* Initial environment variables */ > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + MEM_LAYOUT_ENV_SETTINGS \ > + BOOTENV > + > +/* Link Definitions */ > + > +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 > +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 > +#define CONFIG_SYS_INIT_SP_OFFSET \ > + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) > +#define CONFIG_SYS_INIT_SP_ADDR \ > + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) > + > +#define CONFIG_SYS_SDRAM_BASE 0x40000000 > +#define PHYS_SDRAM 0x40000000 > +#define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */ > + > +#define CONFIG_BAUDRATE 115200 > + > +#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR > + > +/* Monitor Command Prompt */ > +#define CONFIG_SYS_CBSIZE 2048 > +#define CONFIG_SYS_MAXARGS 64 > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ > + sizeof(CONFIG_SYS_PROMPT) + 16) > + > +/* USDHC */ > +#define CONFIG_FSL_USDHC > + > +#define CONFIG_SYS_FSL_USDHC_NUM 2 > +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 > + > +/* I2C */ > +#define CONFIG_SYS_I2C_SPEED 400000 > + > +#endif /* __IMX8MN_VAR_SOM_H */ >
Hi Ariel On Tue, 2021-11-02 at 20:18 -0300, Ariel D'Alessandro wrote: > Add support for iMX8MN VAR-SOM-MX8M-NANO board. Enables support for: > > - 1GiB DDR4 RAM > - 16 GiB eMMC > - SD card > - Gigabit ethernet > - USBOTG1 peripheral - fastboot > > Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com> > --- >  arch/arm/dts/Makefile                        |  1 + >  arch/arm/dts/imx8mn-var-som-u-boot.dtsi      | 220 ++++++++ >  arch/arm/dts/imx8mn-var-som.dts              | 425 ++++++++++++++ >  arch/arm/mach-imx/imx8m/Kconfig              |  9 + >  board/variscite/imx8mn_var_som/Kconfig       | 17 + >  board/variscite/imx8mn_var_som/Makefile      | 12 + >  board/variscite/imx8mn_var_som/ddr4_timing.c | 529 ++++++++++++++++++ >  .../variscite/imx8mn_var_som/imx8mn_var_som.c | 35 ++ >  .../imx8mn_var_som/imximage-8mn-ddr4.cfg     | 12 + >  board/variscite/imx8mn_var_som/spl.c         | 104 ++++ >  configs/imx8mn_var_som_defconfig             | 98 ++++ >  include/configs/imx8mn_var_som.h             | 106 ++++ >  12 files changed, 1568 insertions(+) >  create mode 100644 arch/arm/dts/imx8mn-var-som-u-boot.dtsi >  create mode 100644 arch/arm/dts/imx8mn-var-som.dts >  create mode 100644 board/variscite/imx8mn_var_som/Kconfig >  create mode 100644 board/variscite/imx8mn_var_som/Makefile >  create mode 100644 board/variscite/imx8mn_var_som/ddr4_timing.c >  create mode 100644 board/variscite/imx8mn_var_som/imx8mn_var_som.c >  create mode 100644 board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg >  create mode 100644 board/variscite/imx8mn_var_som/spl.c >  create mode 100644 configs/imx8mn_var_som_defconfig >  create mode 100644 include/configs/imx8mn_var_som.h > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index cc34da7bd83..dfa034be80f 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -901,6 +901,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ >         imx8mn-ddr4-evk.dtb \ >         imx8mq-cm.dtb \ >         imx8mn-evk.dtb \ > +       imx8mn-var-som.dtb \ >         imx8mq-evk.dtb \ >         imx8mm-beacon-kit.dtb \ >         imx8mn-beacon-kit.dtb \ > diff --git a/arch/arm/dts/imx8mn-var-som-u-boot.dtsi b/arch/arm/dts/imx8mn-var-som-u-boot.dtsi > new file mode 100644 > index 00000000000..73df408bc82 > --- /dev/null > +++ b/arch/arm/dts/imx8mn-var-som-u-boot.dtsi > @@ -0,0 +1,220 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2021 Collabora Ltd. > + */ > + > +/ { > +       binman: binman { > +               multiple-images; > +       }; > + > +       wdt-reboot { > +               compatible = "wdt-reboot"; > +               wdt = <&wdog1>; > +               u-boot,dm-spl; > +       }; > +}; > + > +&{/soc@0} { > +       u-boot,dm-pre-reloc; > +       u-boot,dm-spl; > +}; > + > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { > +       u-boot,dm-spl; > +}; > + > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { > +       u-boot,dm-spl; > +}; > + > +&aips1 { > +       u-boot,dm-spl; > +       u-boot,dm-pre-reloc; You might want to consistently order properties alphabetically (e.g. see 3 nodes further up). > +}; > + > +&aips3 { > +       u-boot,dm-spl; > +}; > + > +&aips4 { > +       u-boot,dm-spl; > +}; > + > +&clk { > +       u-boot,dm-spl; > +       u-boot,dm-pre-reloc; Ditto. > +       /delete-property/ assigned-clocks; > +       /delete-property/ assigned-clock-parents; > +       /delete-property/ assigned-clock-rates; > +}; > + > +&gpio1 { > +       u-boot,dm-spl; > +}; > + > +&gpio2 { > +       u-boot,dm-spl; > +}; > + > +&gpio4 { > +       u-boot,dm-spl; > +}; > + > +&i2c1 { > +       u-boot,dm-spl; > +}; > + > +&iomuxc { > +       u-boot,dm-spl; > +}; > + > +&osc_24m { > +       u-boot,dm-spl; > +       u-boot,dm-pre-reloc; Ditto. > +}; > + > +&pinctrl_i2c1 { > +       u-boot,dm-spl; > +}; > + > +&pinctrl_pmic { > +       u-boot,dm-spl; > +}; > + > +&pinctrl_reg_usdhc2_vmmc { > +       u-boot,dm-spl; > +}; > + > +&pinctrl_uart4 { > +       u-boot,dm-spl; > +}; > + > +&pinctrl_usdhc2 { > +       u-boot,dm-spl; > +}; > + > +&pinctrl_usdhc3 { > +       u-boot,dm-spl; > +}; > + > +&pinctrl_wdog { > +       u-boot,dm-spl; > +}; > + > +&uart4 { > +       u-boot,dm-spl; > +}; > + > +&usdhc2 { > +       u-boot,dm-spl; > +}; > + > +&usdhc3 { > +       u-boot,dm-spl; > +}; > + > +&wdog1 { > +       u-boot,dm-spl; > +}; > + > +&binman { > +       u-boot-spl-ddr { > +               filename = "u-boot-spl-ddr.bin"; > +               pad-byte = <0xff>; > +               align-size = <4>; > +               align = <4>; > + > +               u-boot-spl { > +                       align-end = <4>; > +               }; > + > +               blob_1: blob-ext@1 { > +                       filename = "ddr4_imem_1d.bin"; > +                       size = <0x8000>; > +               }; > + > +               blob_2: blob-ext@2 { > +                       filename = "ddr4_dmem_1d.bin"; > +                       size = <0x4000>; > +               }; > + > +               blob_3: blob-ext@3 { > +                       filename = "ddr4_imem_2d.bin"; > +                       size = <0x8000>; > +               }; > + > +               blob_4: blob-ext@4 { > +                       filename = "ddr4_dmem_2d.bin"; > +                       size = <0x4000>; > +               }; > +       }; > + > +       itb { > +               filename = "u-boot.itb"; > + > +               fit { > +                       description = "Configuration to load ATF before U-Boot"; > +                       #address-cells = <1>; > +                       fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; > + > +                       images { > +                               uboot { > +                                       description = "U-Boot (64-bit)"; > +                                       type = "standalone"; > +                                       arch = "arm64"; > +                                       compression = "none"; > +                                       load = <CONFIG_SYS_TEXT_BASE>; > + > +                                       uboot_blob: blob-ext { > +                                               filename = "u-boot-nodtb.bin"; > +                                       }; > +                               }; > + > +                               atf { > +                                       description = "ARM Trusted Firmware"; > +                                       type = "firmware"; > +                                       arch = "arm64"; > +                                       compression = "none"; > +                                       load = <0x960000>; > +                                       entry = <0x960000>; > + > +                                       atf_blob: blob-ext { > +                                               filename = "bl31.bin"; > +                                       }; > +                               }; > + > +                               fdt { > +                                       description = "NAME"; > +                                       type = "flat_dt"; > +                                       compression = "none"; > + > +                                       uboot_fdt_blob: blob-ext { > +                                               filename = "u-boot.dtb"; > +                                       }; > +                               }; > +                       }; > + > +                       configurations { > +                               default = "conf"; > + > +                               conf { > +                                       description = "NAME"; > +                                       firmware = "uboot"; > +                                       loadables = "atf"; > +                                       fdt = "fdt"; > +                               }; > +                       }; > +               }; > +       }; > + > +       flash { > +               mkimage { > +                       args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000"; > + > +                       blob { > +                               filename = "u-boot-spl-ddr.bin"; > +                       }; > +               }; > +       }; > +}; I guess that binman configuration could be unified and further cleaned-up on the Nanos just like what is in- flight for the Mini [1]. > diff --git a/arch/arm/dts/imx8mn-var-som.dts b/arch/arm/dts/imx8mn-var-som.dts > new file mode 100644 > index 00000000000..e094d25af8c > --- /dev/null > +++ b/arch/arm/dts/imx8mn-var-som.dts > @@ -0,0 +1,425 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2021 Collabora Ltd. > + */ > + > +/dts-v1/; > + > +#include "imx8mn.dtsi" > + > +/ { > +       model = "Variscite VAR-SOM-MX8MN module"; > +       compatible = "variscite,var-som-mx8mn", "fsl,imx8mn"; > + > +       chosen { > +               bootargs = "console=ttymxc3,115200 earlycon=ec_imx6q,0x30a60000,115200"; I believe that earlycon stuff after the equal sign is some downstream stuff which may even prohibit any kind of mainline from successfully being run. > +               stdout-path = &uart4; > +       }; > + > +       reg_usdhc2_vmmc: regulator-usdhc2-vmmc { > +               compatible = "regulator-fixed"; > +               pinctrl-names = "default"; > +               pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; > +               regulator-name = "VSD_3V3"; > +               regulator-min-microvolt = <3300000>; > +               regulator-max-microvolt = <3300000>; > +               gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; > +               enable-active-high; > +       }; > + > +       reg_eth_phy: regulator-eth-phy { > +               compatible = "regulator-fixed"; > +               pinctrl-names = "default"; > +               pinctrl-0 = <&pinctrl_reg_eth_phy>; > +               regulator-name = "eth_phy_pwr"; > +               regulator-min-microvolt = <3300000>; > +               regulator-max-microvolt = <3300000>; > +               gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; > +               enable-active-high; > +       }; > +}; > + > +&A53_0 { > +       cpu-supply = <&buck2_reg>; > +}; > + > +&A53_1 { > +       cpu-supply = <&buck2_reg>; > +}; > + > +&A53_2 { > +       cpu-supply = <&buck2_reg>; > +}; > + > +&A53_3 { > +       cpu-supply = <&buck2_reg>; > +}; > + > +&fec1 { > +       pinctrl-names = "default"; > +       pinctrl-0 = <&pinctrl_fec1>; > +       phy-mode = "rgmii"; I assume you do want the MAC to explicitly add RX and TX delays, right? > +       phy-handle = <ðphy>; > +       phy-supply = <®_eth_phy>; > +       phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; > +       phy-reset-duration = <10>; > +       fsl,magic-packet; > +       status = "okay"; > + > +       mdio { > +               #address-cells = <1>; > +               #size-cells = <0>; > + > +               ethphy: ethernet-phy@4 { > +                       compatible = "ethernet-phy-ieee802.3-c22"; > +                       reg = <4>; > +               }; > +       }; > +}; > + > +&i2c1 { > +       clock-frequency = <400000>; > +       pinctrl-names = "default"; > +       pinctrl-0 = <&pinctrl_i2c1>; > +       status = "okay"; > + > +       pmic@4b { > +               compatible = "rohm,bd71847"; > +               reg = <0x4b>; > +               pinctrl-names = "default"; > +               pinctrl-0 = <&pinctrl_pmic>; > +               interrupt-parent = <&gpio2>; > +               interrupts = <8 IRQ_TYPE_LEVEL_LOW>; > +               rohm,reset-snvs-powered; > + > +               regulators { > +                       buck1_reg: BUCK1 { > +                               regulator-name = "buck1"; > +                               regulator-min-microvolt = <700000>; > +                               regulator-max-microvolt = <1300000>; > +                               regulator-boot-on; > +                               regulator-always-on; > +                               regulator-ramp-delay = <1250>; > +                       }; > + > +                       buck2_reg: BUCK2 { > +                               regulator-name = "buck2"; > +                               regulator-min-microvolt = <700000>; > +                               regulator-max-microvolt = <1300000>; > +                               regulator-boot-on; > +                               regulator-always-on; > +                               regulator-ramp-delay = <1250>; > +                               rohm,dvs-run-voltage = <1000000>; > +                               rohm,dvs-idle-voltage = <900000>; > +                       }; > + > +                       buck3_reg: BUCK3 { > +                               regulator-name = "buck3"; > +                               regulator-min-microvolt = <700000>; > +                               regulator-max-microvolt = <1350000>; > +                               regulator-boot-on; > +                               regulator-always-on; > +                       }; > + > +                       buck4_reg: BUCK4 { > +                               regulator-name = "buck4"; > +                               regulator-min-microvolt = <2600000>; > +                               regulator-max-microvolt = <3300000>; > +                               regulator-boot-on; > +                               regulator-always-on; > +                       }; > + > +                       buck5_reg: BUCK5 { > +                               regulator-name = "buck5"; > +                               regulator-min-microvolt = <1605000>; > +                               regulator-max-microvolt = <1995000>; > +                               regulator-boot-on; > +                               regulator-always-on; > +                       }; > + > +                       buck6_reg: BUCK6 { > +                               regulator-name = "buck6"; > +                               regulator-min-microvolt = <800000>; > +                               regulator-max-microvolt = <1400000>; > +                               regulator-boot-on; > +                               regulator-always-on; > +                       }; > + > +                       ldo1_reg: LDO1 { > +                               regulator-name = "ldo1"; > +                               regulator-min-microvolt = <1600000>; > +                               regulator-max-microvolt = <1900000>; > +                               regulator-boot-on; > +                               regulator-always-on; > +                       }; > + > +                       ldo2_reg: LDO2 { > +                               regulator-name = "ldo2"; > +                               regulator-min-microvolt = <800000>; > +                               regulator-max-microvolt = <900000>; > +                               regulator-boot-on; > +                               regulator-always-on; > +                       }; > + > +                       ldo3_reg: LDO3 { > +                               regulator-name = "ldo3"; > +                               regulator-min-microvolt = <1800000>; > +                               regulator-max-microvolt = <3300000>; > +                               regulator-boot-on; > +                               regulator-always-on; > +                       }; > + > +                       ldo4_reg: LDO4 { > +                               regulator-name = "ldo4"; > +                               regulator-min-microvolt = <900000>; > +                               regulator-max-microvolt = <1800000>; > +                               regulator-always-on; > +                       }; > + > +                       ldo5_reg: LDO5 { > +                               regulator-name = "ldo5"; > +                               regulator-min-microvolt = <1800000>; > +                               regulator-max-microvolt = <1800000>; > +                               regulator-always-on; > +                       }; > + > +                       ldo6_reg: LDO6 { > +                               regulator-name = "ldo6"; > +                               regulator-min-microvolt = <900000>; > +                               regulator-max-microvolt = <1800000>; > +                               regulator-boot-on; > +                               regulator-always-on; > +                       }; > +               }; > +       }; > +}; > + > +/* Console */ > +&uart4 { > +       pinctrl-names = "default"; > +       pinctrl-0 = <&pinctrl_uart4>; > +       status = "okay"; > +}; > + > +&usbotg1 { > +       dr_mode = "peripheral"; > +       status = "okay"; > +}; > + > +/* SD */ > +&usdhc2 { > +       assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; > +       assigned-clock-rates = <200000000>; > +       pinctrl-names = "default", "state_100mhz", "state_200mhz"; > +       pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; > +       pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; > +       pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; > +       cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; > +       bus-width = <4>; > +       vmmc-supply = <®_usdhc2_vmmc>; > +       status = "okay"; > +}; > + > +/* eMMC */ > +&usdhc3 { > +       assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; > +       assigned-clock-rates = <400000000>; > +       pinctrl-names = "default", "state_100mhz", "state_200mhz"; > +       pinctrl-0 = <&pinctrl_usdhc3>; > +       pinctrl-1 = <&pinctrl_usdhc3_100mhz>; > +       pinctrl-2 = <&pinctrl_usdhc3_200mhz>; > +       bus-width = <8>; > +       non-removable; > +       status = "okay"; > +}; > + > +&wdog1 { > +       pinctrl-names = "default"; > +       pinctrl-0 = <&pinctrl_wdog>; > +       fsl,ext-reset-output; > +       status = "okay"; > +}; > + > +&iomuxc { > +       pinctrl_fec1: fec1grp { > +               fsl,pins = < > +                       MX8MN_IOMUXC_ENET_MDC_ENET1_MDC                 0x3 > +                       MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO               0x3 > +                       MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f > +                       MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f > +                       MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f > +                       MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f > +                       MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91 > +                       MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91 > +                       MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91 > +                       MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91 > +                       MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f > +                       MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91 > +                       MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91 > +                       MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f > +                       MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9               0x19 > +               >; > +       }; > + > +       pinctrl_i2c1: i2c1grp { > +               fsl,pins = < > +                       MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3 > +                       MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3 > +               >; > +       }; > + > +       pinctrl_pmic: pmicirqgrp { > +               fsl,pins = < > +                       MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8        0x141 > +               >; > +       }; > + > +       pinctrl_reg_eth_phy: regethphygrp { > +               fsl,pins = < > +                       MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9        0x41 > +               >; > +       }; > + > + > +       pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { > +               fsl,pins = < > +                       MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22       0x41 > +               >; > +       }; > + > +       pinctrl_uart4: uart4grp { > +               fsl,pins = < > +                       MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX     0x140 > +                       MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX     0x140 > +               >; > +       }; > + > +       pinctrl_usdhc1: usdhc1grp { > +               fsl,pins = < > +                       MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK         0x190 > +                       MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d0 > +                       MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d0 > +                       MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d0 > +                       MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d0 > +                       MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d0 > +               >; > +       }; > + > +       pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { > +               fsl,pins = < > +                       MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK         0x194 > +                       MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d4 > +                       MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d4 > +                       MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d4 > +                       MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d4 > +                       MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d4 > +               >; > +       }; > + > +       pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { > +               fsl,pins = < > +                       MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK         0x196 > +                       MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d6 > +                       MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d6 > +                       MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d6 > +                       MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d6 > +                       MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d6 > +               >; > +       }; > + > +       pinctrl_usdhc2_gpio: usdhc2gpiogrp { > +               fsl,pins = < > +                       MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10      0x41 > +               >; > +       }; > + > +       pinctrl_usdhc2: usdhc2grp { > +               fsl,pins = < > +                       MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x190 > +                       MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0 > +                       MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0 > +                       MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0 > +                       MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0 > +                       MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0 > +                       MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0 > +               >; > +       }; > + > +       pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { > +               fsl,pins = < > +                       MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x194 > +                       MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4 > +                       MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4 > +                       MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4 > +                       MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4 > +                       MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4 > +                       MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0 > +               >; > +       }; > + > +       pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { > +               fsl,pins = < > +                       MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x196 > +                       MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6 > +                       MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6 > +                       MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6 > +                       MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6 > +                       MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6 > +                       MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0 > +               >; > +       }; > + > +       pinctrl_usdhc3: usdhc3grp { > +               fsl,pins = < > +                       MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK       0x190 > +                       MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d0 > +                       MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d0 > +                       MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d0 > +                       MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d0 > +                       MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d0 > +                       MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d0 > +                       MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d0 > +                       MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d0 > +                       MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d0 > +                       MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x190 > +               >; > +       }; > + > +       pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { > +               fsl,pins = < > +                       MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK       0x194 > +                       MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d4 > +                       MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d4 > +                       MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d4 > +                       MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d4 > +                       MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d4 > +                       MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d4 > +                       MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d4 > +                       MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d4 > +                       MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d4 > +                       MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x194 > +               >; > +       }; > + > +       pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { > +               fsl,pins = < > +                       MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK       0x196 > +                       MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d6 > +                       MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d6 > +                       MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d6 > +                       MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d6 > +                       MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d6 > +                       MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d6 > +                       MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d6 > +                       MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d6 > +                       MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d6 > +                       MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x196 > +               >; > +       }; > + > +       pinctrl_wdog: wdoggrp { > +               fsl,pins = < > +                       MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B    0x166 > +               >; > +       }; > +}; > diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig > index 276b8bd9742..82a5ab8ad00 100644 > --- a/arch/arm/mach-imx/imx8m/Kconfig > +++ b/arch/arm/mach-imx/imx8m/Kconfig > @@ -108,6 +108,14 @@ config TARGET_PICO_IMX8MQ >         select IMX8MQ >         select IMX8M_LPDDR4 >  > +config TARGET_IMX8MN_VAR_SOM > +       bool "imx8mn_var_som" > +       select BINMAN > +       select IMX8MN > +       select SUPPORT_SPL > +       select IMX8M_DDR4 > +       select IMX8M_BOARD_INIT_DRAM > + >  config TARGET_VERDIN_IMX8MM >         bool "Support Toradex Verdin iMX8M Mini module" >         select BINMAN > @@ -171,6 +179,7 @@ source "board/phytec/phycore_imx8mm/Kconfig" >  source "board/phytec/phycore_imx8mp/Kconfig" >  source "board/ronetix/imx8mq-cm/Kconfig" >  source "board/technexion/pico-imx8mq/Kconfig" > +source "board/variscite/imx8mn_var_som/Kconfig" >  source "board/toradex/verdin-imx8mm/Kconfig" >  >  endif > diff --git a/board/variscite/imx8mn_var_som/Kconfig b/board/variscite/imx8mn_var_som/Kconfig > new file mode 100644 > index 00000000000..cfe6fc8c2c7 > --- /dev/null > +++ b/board/variscite/imx8mn_var_som/Kconfig > @@ -0,0 +1,17 @@ > +if TARGET_IMX8MN_VAR_SOM > + > +config SYS_BOARD > +       default "imx8mn_var_som" > + > +config SYS_VENDOR > +       default "variscite" > + > +config SYS_CONFIG_NAME > +       default "imx8mn_var_som" > + > +config IMX_CONFIG > +       default "board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg" > + > +source "board/freescale/common/Kconfig" > + > +endif > diff --git a/board/variscite/imx8mn_var_som/Makefile b/board/variscite/imx8mn_var_som/Makefile > new file mode 100644 > index 00000000000..a8b6a343ffc > --- /dev/null > +++ b/board/variscite/imx8mn_var_som/Makefile > @@ -0,0 +1,12 @@ > +# > +# Copyright 2021 Collabora Ltd. > +# > +# SPDX-License-Identifier:     GPL-2.0+ > +# > + > +obj-y += imx8mn_var_som.o > + > +ifdef CONFIG_SPL_BUILD > +obj-y += spl.o > +obj-y += ddr4_timing.o > +endif > diff --git a/board/variscite/imx8mn_var_som/ddr4_timing.c b/board/variscite/imx8mn_var_som/ddr4_timing.c > new file mode 100644 > index 00000000000..6d3d1805c89 > --- /dev/null > +++ b/board/variscite/imx8mn_var_som/ddr4_timing.c > @@ -0,0 +1,529 @@ > +/* > + * Copyright 2019 NXP > + * > + * SPDX-License-Identifier:    GPL-2.0+ > + * > + * Generated code from MX8M_DDR_tool > + * Align with uboot version: > + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga > + */ > + > +#include <linux/kernel.h> > +#include <asm/arch/ddr.h> > + > +static struct dram_cfg_param ddr_ddrc_cfg[] = { > +       /** Initialize DDRC registers **/ > +       { 0x3d400000, 0x81040010 }, > +       { 0x3d400030, 0x20 }, > +       { 0x3d400034, 0x221306 }, > +       { 0x3d400050, 0x210070 }, > +       { 0x3d400054, 0x10008 }, > +       { 0x3d400060, 0x0 }, > +       { 0x3d400064, 0x9200d2 }, > +       { 0x3d4000c0, 0x0 }, > +       { 0x3d4000c4, 0x1000 }, > +       { 0x3d4000d0, 0xc0030126 }, > +       { 0x3d4000d4, 0x770000 }, > +       { 0x3d4000dc, 0x8340105 }, > +       { 0x3d4000e0, 0x180200 }, > +       { 0x3d4000e4, 0x110000 }, > +       { 0x3d4000e8, 0x2000600 }, > +       { 0x3d4000ec, 0x810 }, > +       { 0x3d4000f0, 0x20 }, > +       { 0x3d4000f4, 0xec7 }, > +       { 0x3d400100, 0x11122914 }, > +       { 0x3d400104, 0x4051c }, > +       { 0x3d400108, 0x608050d }, > +       { 0x3d40010c, 0x400c }, > +       { 0x3d400110, 0x8030409 }, > +       { 0x3d400114, 0x6060403 }, > +       { 0x3d40011c, 0x606 }, > +       { 0x3d400120, 0x5050d08 }, > +       { 0x3d400124, 0x2040a }, > +       { 0x3d40012c, 0x1409010e }, > +       { 0x3d400130, 0x8 }, > +       { 0x3d40013c, 0x0 }, > +       { 0x3d400180, 0x1000040 }, > +       { 0x3d400184, 0x493e }, > +       { 0x3d400190, 0x38b8207 }, > +       { 0x3d400194, 0x2020303 }, > +       { 0x3d400198, 0x7f04011 }, > +       { 0x3d40019c, 0xb0 }, > +       { 0x3d4001a0, 0xe0400018 }, > +       { 0x3d4001a4, 0x48005a }, > +       { 0x3d4001a8, 0x80000000 }, > +       { 0x3d4001b0, 0x1 }, > +       { 0x3d4001b4, 0xb07 }, > +       { 0x3d4001b8, 0x4 }, > +       { 0x3d4001c0, 0x1 }, > +       { 0x3d4001c4, 0x0 }, > +       { 0x3d400200, 0x3f1f }, > +       { 0x3d400204, 0x3f0909 }, > +       { 0x3d400208, 0x700 }, > +       { 0x3d40020c, 0x0 }, > +       { 0x3d400210, 0x1f1f }, > +       { 0x3d400214, 0x7070707 }, > +       { 0x3d400218, 0x7070707 }, > +       { 0x3d40021c, 0xf0f }, > +       { 0x3d400220, 0x3f01 }, > +       { 0x3d400240, 0x6000610 }, > +       { 0x3d400244, 0x1323 }, > +       { 0x3d400400, 0x100 }, > +       { 0x3d400250, 0x317d1a07 }, > +       { 0x3d400254, 0xf }, > +       { 0x3d40025c, 0x2a001b76 }, > +       { 0x3d400264, 0x7300b473 }, > +       { 0x3d40026c, 0x30000e06 }, > +       { 0x3d400300, 0x14 }, > +       { 0x3d40036c, 0x10 }, > +       { 0x3d400404, 0x13193 }, > +       { 0x3d400408, 0x6096 }, > +       { 0x3d400490, 0x1 }, > +       { 0x3d400494, 0x2000c00 }, > +       { 0x3d400498, 0x3c00db }, > +       { 0x3d40049c, 0x100009 }, > +       { 0x3d4004a0, 0x2 }, > +       { 0x3d402050, 0x210070 }, > +       { 0x3d402064, 0x40005e }, > +       { 0x3d4020dc, 0x40105 }, > +       { 0x3d4020e0, 0x0 }, > +       { 0x3d4020e8, 0x2000600 }, > +       { 0x3d4020ec, 0x10 }, > +       { 0x3d402100, 0xb081209 }, > +       { 0x3d402104, 0x2020d }, > +       { 0x3d402108, 0x5050309 }, > +       { 0x3d40210c, 0x400c }, > +       { 0x3d402110, 0x5030206 }, > +       { 0x3d402114, 0x3030202 }, > +       { 0x3d40211c, 0x303 }, > +       { 0x3d402120, 0x3030d04 }, > +       { 0x3d402124, 0x20208 }, > +       { 0x3d40212c, 0x1005010e }, > +       { 0x3d402130, 0x8 }, > +       { 0x3d40213c, 0x0 }, > +       { 0x3d402180, 0x1000040 }, > +       { 0x3d402190, 0x3858204 }, > +       { 0x3d402194, 0x2020303 }, > +       { 0x3d4021b4, 0x504 }, > +       { 0x3d4021b8, 0x4 }, > +       { 0x3d402240, 0x6000604 }, > +       { 0x3d4020f4, 0xec7 }, > +}; > + > +/* PHY Initialize Configuration */ > +static struct dram_cfg_param ddr_ddrphy_cfg[] = { > +       { 0x1005f, 0x2fd }, > +       { 0x1015f, 0x2fd }, > +       { 0x1105f, 0x2fd }, > +       { 0x1115f, 0x2fd }, > +       { 0x11005f, 0x2fd }, > +       { 0x11015f, 0x2fd }, > +       { 0x11105f, 0x2fd }, > +       { 0x11115f, 0x2fd }, > +       { 0x55, 0x355 }, > +       { 0x1055, 0x355 }, > +       { 0x2055, 0x355 }, > +       { 0x3055, 0x355 }, > +       { 0x4055, 0x55 }, > +       { 0x5055, 0x55 }, > +       { 0x6055, 0x355 }, > +       { 0x7055, 0x355 }, > +       { 0x8055, 0x355 }, > +       { 0x9055, 0x355 }, > +       { 0x200c5, 0xa }, > +       { 0x1200c5, 0x6 }, > +       { 0x2002e, 0x2 }, > +       { 0x12002e, 0x1 }, > +       { 0x20024, 0x8 }, > +       { 0x2003a, 0x2 }, > +       { 0x120024, 0x8 }, > +       { 0x2003a, 0x2 }, > +       { 0x20056, 0x6 }, > +       { 0x120056, 0xa }, > +       { 0x1004d, 0x1a }, > +       { 0x1014d, 0x1a }, > +       { 0x1104d, 0x1a }, > +       { 0x1114d, 0x1a }, > +       { 0x11004d, 0x1a }, > +       { 0x11014d, 0x1a }, > +       { 0x11104d, 0x1a }, > +       { 0x11114d, 0x1a }, > +       { 0x10049, 0xe38 }, > +       { 0x10149, 0xe38 }, > +       { 0x11049, 0xe38 }, > +       { 0x11149, 0xe38 }, > +       { 0x110049, 0xe38 }, > +       { 0x110149, 0xe38 }, > +       { 0x111049, 0xe38 }, > +       { 0x111149, 0xe38 }, > +       { 0x43, 0x63 }, > +       { 0x1043, 0x63 }, > +       { 0x2043, 0x63 }, > +       { 0x3043, 0x63 }, > +       { 0x4043, 0x63 }, > +       { 0x5043, 0x63 }, > +       { 0x6043, 0x63 }, > +       { 0x7043, 0x63 }, > +       { 0x8043, 0x63 }, > +       { 0x9043, 0x63 }, > +       { 0x20018, 0x1 }, > +       { 0x20075, 0x2 }, > +       { 0x20050, 0x0 }, > +       { 0x20008, 0x258 }, > +       { 0x120008, 0x10a }, > +       { 0x20088, 0x9 }, > +       { 0x200b2, 0x268 }, > +       { 0x10043, 0x5b1 }, > +       { 0x10143, 0x5b1 }, > +       { 0x11043, 0x5b1 }, > +       { 0x11143, 0x5b1 }, > +       { 0x1200b2, 0x268 }, > +       { 0x110043, 0x5b1 }, > +       { 0x110143, 0x5b1 }, > +       { 0x111043, 0x5b1 }, > +       { 0x111143, 0x5b1 }, > +       { 0x200fa, 0x1 }, > +       { 0x1200fa, 0x1 }, > +       { 0x20019, 0x5 }, > +       { 0x120019, 0x5 }, > +       { 0x200f0, 0x5555 }, > +       { 0x200f1, 0x5555 }, > +       { 0x200f2, 0x5555 }, > +       { 0x200f3, 0x5555 }, > +       { 0x200f4, 0x5555 }, > +       { 0x200f5, 0x5555 }, > +       { 0x200f6, 0x5555 }, > +       { 0x200f7, 0xf000 }, > +       { 0x20025, 0x0 }, > +       { 0x2002d, 0x0 }, > +       { 0x12002d, 0x0 }, > +       { 0x2005b, 0x7529 }, > +       { 0x2005c, 0x0 }, > +       { 0x200c7, 0x21 }, > +       { 0x200ca, 0x24 }, > +       { 0x200cc, 0x1f7 }, > +       { 0x1200c7, 0x21 }, > +       { 0x1200ca, 0x24 }, > +       { 0x1200cc, 0x1f7 }, > +       { 0x2007d, 0x212 }, > +       { 0x12007d, 0x212 }, > +       { 0x2007c, 0x61 }, > +       { 0x12007c, 0x61 }, > +       { 0x1004a, 0x500 }, > +       { 0x1104a, 0x500 }, > +       { 0x2002c, 0x0 }, > +}; > + > +/* P0 message block parameter for training firmware */ > +static struct dram_cfg_param ddr_fsp0_cfg[] = { > +       { 0xd0000, 0x0 }, > +       { 0x54003, 0x960 }, > +       { 0x54004, 0x2 }, > +       { 0x54005, 0x2830 }, > +       { 0x54006, 0x25e }, > +       { 0x54007, 0x1000 }, > +       { 0x54008, 0x101 }, > +       { 0x5400b, 0x31f }, > +       { 0x5400c, 0xc8 }, > +       { 0x5400d, 0x100 }, > +       { 0x54012, 0x1 }, > +       { 0x5402f, 0x834 }, > +       { 0x54030, 0x105 }, > +       { 0x54031, 0x18 }, > +       { 0x54032, 0x200 }, > +       { 0x54033, 0x200 }, > +       { 0x54034, 0x600 }, > +       { 0x54035, 0x810 }, > +       { 0x54036, 0x101 }, > +       { 0x5403f, 0x1221 }, > +       { 0x541fc, 0x100 }, > +       { 0xd0000, 0x1 }, > +}; > + > +/* P1 message block parameter for training firmware */ > +static struct dram_cfg_param ddr_fsp1_cfg[] = { > +       { 0xd0000, 0x0 }, > +       { 0x54002, 0x1 }, > +       { 0x54003, 0x42a }, > +       { 0x54004, 0x2 }, > +       { 0x54005, 0x2830 }, > +       { 0x54006, 0x25e }, > +       { 0x54007, 0x1000 }, > +       { 0x54008, 0x101 }, > +       { 0x5400b, 0x21f }, > +       { 0x5400c, 0xc8 }, > +       { 0x5400d, 0x100 }, > +       { 0x54012, 0x1 }, > +       { 0x5402f, 0x4 }, > +       { 0x54030, 0x105 }, > +       { 0x54033, 0x200 }, > +       { 0x54034, 0x600 }, > +       { 0x54035, 0x10 }, > +       { 0x54036, 0x101 }, > +       { 0x5403f, 0x1221 }, > +       { 0x541fc, 0x100 }, > +       { 0xd0000, 0x1 }, > +}; > + > +/* P0 2D message block parameter for training firmware */ > +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { > +       { 0xd0000, 0x0 }, > +       { 0x54003, 0x960 }, > +       { 0x54004, 0x2 }, > +       { 0x54005, 0x2830 }, > +       { 0x54006, 0x25e }, > +       { 0x54007, 0x1000 }, > +       { 0x54008, 0x101 }, > +       { 0x5400b, 0x61 }, > +       { 0x5400c, 0xc8 }, > +       { 0x5400d, 0x100 }, > +       { 0x5400e, 0x1f7f }, > +       { 0x54012, 0x1 }, > +       { 0x5402f, 0x834 }, > +       { 0x54030, 0x105 }, > +       { 0x54031, 0x18 }, > +       { 0x54032, 0x200 }, > +       { 0x54033, 0x200 }, > +       { 0x54034, 0x600 }, > +       { 0x54035, 0x810 }, > +       { 0x54036, 0x101 }, > +       { 0x5403f, 0x1221 }, > +       { 0x541fc, 0x100 }, > +       { 0xd0000, 0x1 }, > +}; > + > +/* DRAM PHY init engine image */ > +static struct dram_cfg_param ddr_phy_pie[] = { > +       { 0xd0000, 0x0 }, > +       { 0x90000, 0x10 }, > +       { 0x90001, 0x400 }, > +       { 0x90002, 0x10e }, > +       { 0x90003, 0x0 }, > +       { 0x90004, 0x0 }, > +       { 0x90005, 0x8 }, > +       { 0x90029, 0xb }, > +       { 0x9002a, 0x480 }, > +       { 0x9002b, 0x109 }, > +       { 0x9002c, 0x8 }, > +       { 0x9002d, 0x448 }, > +       { 0x9002e, 0x139 }, > +       { 0x9002f, 0x8 }, > +       { 0x90030, 0x478 }, > +       { 0x90031, 0x109 }, > +       { 0x90032, 0x2 }, > +       { 0x90033, 0x10 }, > +       { 0x90034, 0x139 }, > +       { 0x90035, 0xb }, > +       { 0x90036, 0x7c0 }, > +       { 0x90037, 0x139 }, > +       { 0x90038, 0x44 }, > +       { 0x90039, 0x633 }, > +       { 0x9003a, 0x159 }, > +       { 0x9003b, 0x14f }, > +       { 0x9003c, 0x630 }, > +       { 0x9003d, 0x159 }, > +       { 0x9003e, 0x47 }, > +       { 0x9003f, 0x633 }, > +       { 0x90040, 0x149 }, > +       { 0x90041, 0x4f }, > +       { 0x90042, 0x633 }, > +       { 0x90043, 0x179 }, > +       { 0x90044, 0x8 }, > +       { 0x90045, 0xe0 }, > +       { 0x90046, 0x109 }, > +       { 0x90047, 0x0 }, > +       { 0x90048, 0x7c8 }, > +       { 0x90049, 0x109 }, > +       { 0x9004a, 0x0 }, > +       { 0x9004b, 0x1 }, > +       { 0x9004c, 0x8 }, > +       { 0x9004d, 0x0 }, > +       { 0x9004e, 0x45a }, > +       { 0x9004f, 0x9 }, > +       { 0x90050, 0x0 }, > +       { 0x90051, 0x448 }, > +       { 0x90052, 0x109 }, > +       { 0x90053, 0x40 }, > +       { 0x90054, 0x633 }, > +       { 0x90055, 0x179 }, > +       { 0x90056, 0x1 }, > +       { 0x90057, 0x618 }, > +       { 0x90058, 0x109 }, > +       { 0x90059, 0x40c0 }, > +       { 0x9005a, 0x633 }, > +       { 0x9005b, 0x149 }, > +       { 0x9005c, 0x8 }, > +       { 0x9005d, 0x4 }, > +       { 0x9005e, 0x48 }, > +       { 0x9005f, 0x4040 }, > +       { 0x90060, 0x633 }, > +       { 0x90061, 0x149 }, > +       { 0x90062, 0x0 }, > +       { 0x90063, 0x4 }, > +       { 0x90064, 0x48 }, > +       { 0x90065, 0x40 }, > +       { 0x90066, 0x633 }, > +       { 0x90067, 0x149 }, > +       { 0x90068, 0x10 }, > +       { 0x90069, 0x4 }, > +       { 0x9006a, 0x18 }, > +       { 0x9006b, 0x0 }, > +       { 0x9006c, 0x4 }, > +       { 0x9006d, 0x78 }, > +       { 0x9006e, 0x549 }, > +       { 0x9006f, 0x633 }, > +       { 0x90070, 0x159 }, > +       { 0x90071, 0xd49 }, > +       { 0x90072, 0x633 }, > +       { 0x90073, 0x159 }, > +       { 0x90074, 0x94a }, > +       { 0x90075, 0x633 }, > +       { 0x90076, 0x159 }, > +       { 0x90077, 0x441 }, > +       { 0x90078, 0x633 }, > +       { 0x90079, 0x149 }, > +       { 0x9007a, 0x42 }, > +       { 0x9007b, 0x633 }, > +       { 0x9007c, 0x149 }, > +       { 0x9007d, 0x1 }, > +       { 0x9007e, 0x633 }, > +       { 0x9007f, 0x149 }, > +       { 0x90080, 0x0 }, > +       { 0x90081, 0xe0 }, > +       { 0x90082, 0x109 }, > +       { 0x90083, 0xa }, > +       { 0x90084, 0x10 }, > +       { 0x90085, 0x109 }, > +       { 0x90086, 0x9 }, > +       { 0x90087, 0x3c0 }, > +       { 0x90088, 0x149 }, > +       { 0x90089, 0x9 }, > +       { 0x9008a, 0x3c0 }, > +       { 0x9008b, 0x159 }, > +       { 0x9008c, 0x18 }, > +       { 0x9008d, 0x10 }, > +       { 0x9008e, 0x109 }, > +       { 0x9008f, 0x0 }, > +       { 0x90090, 0x3c0 }, > +       { 0x90091, 0x109 }, > +       { 0x90092, 0x18 }, > +       { 0x90093, 0x4 }, > +       { 0x90094, 0x48 }, > +       { 0x90095, 0x18 }, > +       { 0x90096, 0x4 }, > +       { 0x90097, 0x58 }, > +       { 0x90098, 0xb }, > +       { 0x90099, 0x10 }, > +       { 0x9009a, 0x109 }, > +       { 0x9009b, 0x1 }, > +       { 0x9009c, 0x10 }, > +       { 0x9009d, 0x109 }, > +       { 0x9009e, 0x5 }, > +       { 0x9009f, 0x7c0 }, > +       { 0x900a0, 0x109 }, > +       { 0x900a1, 0x0 }, > +       { 0x900a2, 0x8140 }, > +       { 0x900a3, 0x10c }, > +       { 0x900a4, 0x10 }, > +       { 0x900a5, 0x8138 }, > +       { 0x900a6, 0x10c }, > +       { 0x900a7, 0x8 }, > +       { 0x900a8, 0x7c8 }, > +       { 0x900a9, 0x101 }, > +       { 0x900aa, 0x8 }, > +       { 0x900ab, 0x448 }, > +       { 0x900ac, 0x109 }, > +       { 0x900ad, 0xf }, > +       { 0x900ae, 0x7c0 }, > +       { 0x900af, 0x109 }, > +       { 0x900b0, 0x47 }, > +       { 0x900b1, 0x630 }, > +       { 0x900b2, 0x109 }, > +       { 0x900b3, 0x8 }, > +       { 0x900b4, 0x618 }, > +       { 0x900b5, 0x109 }, > +       { 0x900b6, 0x8 }, > +       { 0x900b7, 0xe0 }, > +       { 0x900b8, 0x109 }, > +       { 0x900b9, 0x0 }, > +       { 0x900ba, 0x7c8 }, > +       { 0x900bb, 0x109 }, > +       { 0x900bc, 0x8 }, > +       { 0x900bd, 0x8140 }, > +       { 0x900be, 0x10c }, > +       { 0x900bf, 0x0 }, > +       { 0x900c0, 0x1 }, > +       { 0x900c1, 0x8 }, > +       { 0x900c2, 0x8 }, > +       { 0x900c3, 0x4 }, > +       { 0x900c4, 0x8 }, > +       { 0x900c5, 0x8 }, > +       { 0x900c6, 0x7c8 }, > +       { 0x900c7, 0x101 }, > +       { 0x90006, 0x0 }, > +       { 0x90007, 0x0 }, > +       { 0x90008, 0x8 }, > +       { 0x90009, 0x0 }, > +       { 0x9000a, 0x0 }, > +       { 0x9000b, 0x0 }, > +       { 0xd00e7, 0x400 }, > +       { 0x90017, 0x0 }, > +       { 0x90026, 0x2b }, > +       { 0x2000b, 0x4b }, > +       { 0x2000c, 0x96 }, > +       { 0x2000d, 0x5dc }, > +       { 0x2000e, 0x2c }, > +       { 0x12000b, 0x21 }, > +       { 0x12000c, 0x42 }, > +       { 0x12000d, 0x29a }, > +       { 0x12000e, 0x21 }, > +       { 0x9000c, 0x0 }, > +       { 0x9000d, 0x173 }, > +       { 0x9000e, 0x60 }, > +       { 0x9000f, 0x6110 }, > +       { 0x90010, 0x2152 }, > +       { 0x90011, 0xdfbd }, > +       { 0x90012, 0xffff }, > +       { 0x90013, 0x6152 }, > +       { 0x20089, 0x1 }, > +       { 0x20088, 0x19 }, > +       { 0xc0080, 0x0 }, > +       { 0xd0000, 0x1 }, > +}; > + > +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { > +       { > +               /* P0 2400mts 1D */ > +               .drate = 2400, > +               .fw_type = FW_1D_IMAGE, > +               .fsp_cfg = ddr_fsp0_cfg, > +               .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), > +       }, > +       { > +               /* P1 1066mts 1D */ > +               .drate = 1066, > +               .fw_type = FW_1D_IMAGE, > +               .fsp_cfg = ddr_fsp1_cfg, > +               .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), > +       }, > +       { > +               /* P0 2400mts 2D */ > +               .drate = 2400, > +               .fw_type = FW_2D_IMAGE, > +               .fsp_cfg = ddr_fsp0_2d_cfg, > +               .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), > +       }, > +}; > + > +/* ddr timing config params */ > +struct dram_timing_info dram_timing = { > +       .ddrc_cfg = ddr_ddrc_cfg, > +       .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), > +       .ddrphy_cfg = ddr_ddrphy_cfg, > +       .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), > +       .fsp_msg = ddr_dram_fsp_msg, > +       .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), > +       .ddrphy_pie = ddr_phy_pie, > +       .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), > +       .fsp_table = { 2400, 1066, }, > +}; > diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c b/board/variscite/imx8mn_var_som/imx8mn_var_som.c > new file mode 100644 > index 00000000000..1d2f8a40590 > --- /dev/null > +++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c > @@ -0,0 +1,35 @@ > +/* > + * Copyright 2021 Collabora Ltd. > + * > + * SPDX-License-Identifier:    GPL-2.0+ > + */ > + > +#include <common.h> > +#include <env.h> > +#include <asm/io.h> > + > +#if IS_ENABLED(CONFIG_FEC_MXC) > +static int setup_fec(void) > +{ > +       struct iomuxc_gpr_base_regs *gpr = > +               (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; > + > +       /* Use 125M anatop REF_CLK1 for ENET1, not from external */ > +       clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); > + > +       return 0; > +} > +#endif > + > +int board_init(void) > +{ > +       if (IS_ENABLED(CONFIG_FEC_MXC)) > +               setup_fec(); > + > +       return 0; > +} > + > +int board_mmc_get_env_dev(int devno) > +{ > +       return devno; > +} > diff --git a/board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg b/board/variscite/imx8mn_var_som/imximage- > 8mn-ddr4.cfg > new file mode 100644 > index 00000000000..a24856eb631 > --- /dev/null > +++ b/board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg I believe usually that file was just called imximage.cfg. I am not against a target specific name but then your name does not really seem that target specific. > @@ -0,0 +1,12 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright 2021 Collabora Ltd. > + */ > + > +#define __ASSEMBLY__ > + > +FIT > +ROM_VERSION v2 > +BOOT_FROM sd > +LOADER u-boot-spl-ddr.bin 0x912000 > +SECOND_LOADER u-boot.itb 0x40200000 0x60000 Not sure what exactly that SECOND_LOADER achieves. Isn't that nowadays handled by binman? > diff --git a/board/variscite/imx8mn_var_som/spl.c b/board/variscite/imx8mn_var_som/spl.c > new file mode 100644 > index 00000000000..f7e17f65127 > --- /dev/null > +++ b/board/variscite/imx8mn_var_som/spl.c > @@ -0,0 +1,104 @@ > +/* > + * Copyright 2021 Collabora Ltd. > + * > + * SPDX-License-Identifier:    GPL-2.0+ > + */ > + > +#include <hang.h> > +#include <init.h> > +#include <spl.h> > +#include <asm/arch/clock.h> > +#include <asm/arch/ddr.h> > +#include <asm/arch/imx8mn_pins.h> > +#include <asm/arch/sys_proto.h> > +#include <asm/mach-imx/boot_mode.h> > +#include <asm/mach-imx/gpio.h> > + That newline does not really serve any purpose. > +#include <dm/device.h> > +#include <dm/uclass.h> > + > +int spl_board_boot_device(enum boot_device boot_dev_spl) > +{ > +       return BOOT_DEVICE_BOOTROM; > +} > + > +void spl_dram_init(void) > +{ > +       ddr_init(&dram_timing); > +} > + > +void spl_board_init(void) > +{ > +       struct udevice *dev; > +       int ret; > + > +       debug("Normal Boot\n"); > + > +       ret = uclass_get_device_by_name(UCLASS_CLK, > +                                       "clock-controller@30380000", > +                                       &dev); > +       if (ret < 0) > +               puts("Failed to find clock node. Check device tree\n"); > +} > + > +#ifdef CONFIG_SPL_LOAD_FIT > +int board_fit_config_name_match(const char *name) > +{ > +       /* Just empty function now - can't decide what to choose */ > +       debug("%s: %s\n", __func__, name); > + > +       return 0; > +} > +#endif > + > +#define UART_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_FSEL1) > +#define WDOG_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) > + > +static iomux_v3_cfg_t const uart_pads[] = { Didn't checkpatch suggest to put that const after static? 0 errors, 11 warnings, 2 checks for 0001-imx8mn_var_som-Add-support-for-Variscite-VAR-SOM-MX8.patch: <patch>:56: warning: added, moved or deleted file(s), does MAINTAINERS need updating? arch/arm/dts/imx8mn-var-som.dts:283: check: Please don't use multiple blank lines board/variscite/imx8mn_var_som/ddr4_timing.c:1: warning: Missing or malformed SPDX-License-Identifier tag in line 1 board/variscite/imx8mn_var_som/ddr4_timing.c:4: warning: Misplaced SPDX-License-Identifier tag - use line 1 instead board/variscite/imx8mn_var_som/imx8mn_var_som.c:1: warning: Missing or malformed SPDX-License-Identifier tag in line 1 board/variscite/imx8mn_var_som/imx8mn_var_som.c:4: warning: Misplaced SPDX-License-Identifier tag - use line 1 instead board/variscite/imx8mn_var_som/imx8mn_var_som.c:11: warning: Use 'if (IS_ENABLED(CONFIG...))' instead of '#if or #ifdef' where possible board/variscite/imx8mn_var_som/spl.c:1: warning: Missing or malformed SPDX-License-Identifier tag in line 1 board/variscite/imx8mn_var_som/spl.c:4: warning: Misplaced SPDX-License-Identifier tag - use line 1 instead board/variscite/imx8mn_var_som/spl.c:44: warning: Use 'if (IS_ENABLED(CONFIG...))' instead of '#if or #ifdef' where possible board/variscite/imx8mn_var_som/spl.c:57: warning: Move const after static - use 'static const iomux_v3_cfg_t' board/variscite/imx8mn_var_som/spl.c:62: warning: Move const after static - use 'static const iomux_v3_cfg_t' include/configs/imx8mn_var_som.h:37: check: Macro argument reuse 'func' - possible side-effects? checkpatch.pl found 0 error(s), 11 warning(s), 2 checks(s) You might want to address all of those suggestions (;-p). > +       IMX8MN_PAD_UART4_RXD__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), > +       IMX8MN_PAD_UART4_TXD__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), > +}; > + > +static iomux_v3_cfg_t const wdog_pads[] = { Ditto. > +       IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), > +}; > + > +int board_early_init_f(void) > +{ > +       struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; > + > +       imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); > +       set_wdog_reset(wdog); > + > +       imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); > +       init_uart_clk(3); > + > +       return 0; > +} > + > +void board_init_f(ulong dummy) > +{ > +       int ret; > + > +       /* Clear the BSS. */ > +       memset(__bss_start, 0, __bss_end - __bss_start); > + > +       arch_cpu_init(); > + > +       board_early_init_f(); > + > +       timer_init(); > + > +       preloader_console_init(); > + > +       ret = spl_init(); > +       if (ret) { > +               debug("spl_init() failed: %d\n", ret); > +               hang(); > +       } > + > +       /* DDR initialization */ > +       spl_dram_init(); > + > +       board_init_r(NULL, 0); > +} > diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig > new file mode 100644 > index 00000000000..41d317fd5b0 > --- /dev/null > +++ b/configs/imx8mn_var_som_defconfig > @@ -0,0 +1,98 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_IMX8M=y > +CONFIG_SYS_TEXT_BASE=0x40200000 > +CONFIG_SYS_MALLOC_LEN=0x2000000 > +CONFIG_SYS_MALLOC_F_LEN=0x10000 > +CONFIG_SPL_GPIO=y > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > +CONFIG_NR_DRAM_BANKS=1 > +CONFIG_ENV_SIZE=0x2000 > +CONFIG_ENV_OFFSET=0xFFFFDE00 > +CONFIG_DM_GPIO=y > +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-var-som" > +CONFIG_SPL_TEXT_BASE=0x912000 > +CONFIG_TARGET_IMX8MN_VAR_SOM=y > +CONFIG_SPL_MMC=y > +CONFIG_SPL_SERIAL=y > +CONFIG_SPL_DRIVERS_MISC=y > +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 > +CONFIG_SPL=y > +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 > +CONFIG_DISTRO_DEFAULTS=y > +CONFIG_SYS_LOAD_ADDR=0x40480000 > +CONFIG_FIT=y > +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 > +CONFIG_SPL_LOAD_FIT=y > +# CONFIG_USE_SPL_FIT_GENERATOR is not set > +CONFIG_OF_SYSTEM_SETUP=y > +CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-var-som-symphony.dtb" > +CONFIG_ARCH_MISC_INIT=y > +CONFIG_SPL_BOARD_INIT=y > +CONFIG_SPL_BOOTROM_SUPPORT=y > +CONFIG_SPL_SEPARATE_BSS=y > +CONFIG_SPL_I2C=y > +CONFIG_SPL_POWER=y > +CONFIG_SPL_WATCHDOG=y > +CONFIG_SYS_PROMPT="> " > +CONFIG_CMD_FUSE=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_USB=y > +CONFIG_CMD_USB_MASS_STORAGE=y > +CONFIG_OF_CONTROL=y > +CONFIG_SPL_OF_CONTROL=y > +CONFIG_ENV_IS_IN_MMC=y > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y > +CONFIG_SYS_MMC_ENV_DEV=2 > +CONFIG_SYS_MMC_ENV_PART=1 > +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y > +CONFIG_NET_RANDOM_ETHADDR=y > +CONFIG_SPL_DM=y > +CONFIG_REGMAP=y > +CONFIG_SYSCON=y > +CONFIG_SPL_CLK_COMPOSITE_CCF=y > +CONFIG_CLK_COMPOSITE_CCF=y > +CONFIG_SPL_CLK_IMX8MN=y > +CONFIG_CLK_IMX8MN=y > +CONFIG_USB_FUNCTION_FASTBOOT=y > +CONFIG_FASTBOOT_BUF_ADDR=0x40480000 > +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 > +CONFIG_FASTBOOT_FLASH=y > +CONFIG_FASTBOOT_UUU_SUPPORT=y > +CONFIG_FASTBOOT_FLASH_MMC_DEV=2 > +CONFIG_MXC_GPIO=y > +CONFIG_DM_I2C=y > +CONFIG_SUPPORT_EMMC_BOOT=y > +CONFIG_MMC_IO_VOLTAGE=y > +CONFIG_MMC_UHS_SUPPORT=y > +CONFIG_MMC_HS400_ES_SUPPORT=y > +CONFIG_MMC_HS400_SUPPORT=y > +CONFIG_FSL_ESDHC_IMX=y > +CONFIG_PHYLIB=y > +CONFIG_PHY_ATHEROS=y > +CONFIG_DM_ETH=y > +CONFIG_PHY_GIGE=y > +CONFIG_FEC_MXC=y > +CONFIG_MII=y > +CONFIG_PINCTRL=y > +CONFIG_SPL_PINCTRL=y > +CONFIG_PINCTRL_IMX8M=y > +CONFIG_DM_PMIC=y > +CONFIG_DM_PMIC_BD71837=y > +CONFIG_SPL_DM_PMIC_BD71837=y > +CONFIG_DM_REGULATOR=y > +CONFIG_DM_REGULATOR_FIXED=y > +CONFIG_DM_REGULATOR_GPIO=y > +CONFIG_MXC_UART=y > +CONFIG_SYSRESET=y > +CONFIG_SYSRESET_PSCI=y > +CONFIG_SYSRESET_WATCHDOG=y > +CONFIG_USB=y > +CONFIG_USB_EHCI_HCD=y > +CONFIG_USB_GADGET=y > +CONFIG_USB_GADGET_MANUFACTURER="FSL" > +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 > +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 > +CONFIG_CI_UDC=y > +CONFIG_IMX_WATCHDOG=y > +CONFIG_OF_LIBFDT_OVERLAY=y > diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h > new file mode 100644 > index 00000000000..0ba1af135ff > --- /dev/null > +++ b/include/configs/imx8mn_var_som.h > @@ -0,0 +1,106 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright 2021 Collabora Ltd. > + */ > + > +#ifndef __IMX8MN_VAR_SOM_H > +#define __IMX8MN_VAR_SOM_H > + > +#include <linux/sizes.h> > +#include <linux/stringify.h> > +#include <asm/arch/imx-regs.h> > + > +#define CONFIG_SYS_BOOTM_LEN           (32 * SZ_1M) > + > +#define CONFIG_SPL_MAX_SIZE            (148 * SZ_1K) > +#define CONFIG_SYS_MONITOR_LEN         SZ_512K > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR                0x300 > +#define CONFIG_SYS_UBOOT_BASE  \ > +       (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) > + > +#ifdef CONFIG_SPL_BUILD > + > +#define CONFIG_SPL_STACK               0x980000 > +#define CONFIG_SPL_BSS_START_ADDR      0x950000 > +#define CONFIG_SPL_BSS_MAX_SIZE                SZ_8K   /* 8 KB */ Once using those SZ macros those comments don't really make much sense any longer. > +#define CONFIG_SYS_SPL_MALLOC_START    0x42200000 > +#define CONFIG_SYS_SPL_MALLOC_SIZE     SZ_512K /* 512 KB */ Ditto. > + > +/* For RAW image gives a error info not panic */ > +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE > + > +#endif /* CONFIG_SPL_BUILD */ > + > +#ifndef CONFIG_SPL_BUILD > + > +#define BOOT_TARGET_DEVICES(func) \ > +       func(MMC, mmc, 1) \ > +       func(MMC, mmc, 2) \ > +       func(MMC, mmc, 0) \ > +       func(PXE, pxe, na) \ > +       func(DHCP, dhcp, na) \ > + > +#include <config_distro_bootcmd.h> > + > +#endif /* !CONFIG_SPL_BUILD */ > + > +/* ENET */ > +#if defined(CONFIG_FEC_MXC) > +#define CONFIG_ETHPRIME                        "FEC" > +#define CONFIG_FEC_XCV_TYPE            RGMII > +#endif /* CONFIG_FEC_MXC */ > + > +#define MEM_LAYOUT_ENV_SETTINGS \ > +       "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ > +       "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ > +       "ramdisk_addr_r=0x43800000\0" \ > +       "fdt_addr_r=0x43000000\0" \ > +       "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ > +       "fastboot_partition_alias_all=" \ > +               __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) ".0:0\0" \ > +       "fastboot_partition_alias_bootloader=" \ > +               __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) ".1:0\0" \ > +       "emmc_dev=" __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) "\0" \ > +       "emmc_ack=1\0" \ > +       "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ > + > +/* Initial environment variables */ > +#define CONFIG_EXTRA_ENV_SETTINGS \ > +       MEM_LAYOUT_ENV_SETTINGS \ > +       BOOTENV > + > +/* Link Definitions */ > + > +#define CONFIG_SYS_INIT_RAM_ADDR       0x40000000 > +#define CONFIG_SYS_INIT_RAM_SIZE       0x80000 SZ_512K > +#define CONFIG_SYS_INIT_SP_OFFSET \ > +       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) > +#define CONFIG_SYS_INIT_SP_ADDR \ > +       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) > + > +#define CONFIG_SYS_SDRAM_BASE          0x40000000 > +#define PHYS_SDRAM                     0x40000000 > +#define PHYS_SDRAM_SIZE                        SZ_1G /* 1GB DDR */ > + > +#define CONFIG_BAUDRATE                        115200 > + > +#define CONFIG_MXC_UART_BASE           UART4_BASE_ADDR > + > +/* Monitor Command Prompt */ > +#define CONFIG_SYS_CBSIZE              2048 SZ_2K > +#define CONFIG_SYS_MAXARGS             64 > +#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE > +#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \ > +                                       sizeof(CONFIG_SYS_PROMPT) + 16) > + > +/* USDHC */ > +#define CONFIG_FSL_USDHC > + > +#define CONFIG_SYS_FSL_USDHC_NUM       2 > +#define CONFIG_SYS_FSL_ESDHC_ADDR      0 > + > +/* I2C */ > +#define CONFIG_SYS_I2C_SPEED           400000 > + > +#endif /* __IMX8MN_VAR_SOM_H */ [1] https://marc.info/?l=u-boot&m=163494450717531 Cheers Marcel
Hi Marcel, On 11/3/21 6:22 PM, Marcel Ziswiler wrote: > Hi Ariel > > On Tue, 2021-11-02 at 20:18 -0300, Ariel D'Alessandro wrote: >> Add support for iMX8MN VAR-SOM-MX8M-NANO board. Enables support for: >> >> - 1GiB DDR4 RAM >> - 16 GiB eMMC >> - SD card >> - Gigabit ethernet >> - USBOTG1 peripheral - fastboot >> >> Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com> >> --- >>  arch/arm/dts/Makefile                        |  1 + >>  arch/arm/dts/imx8mn-var-som-u-boot.dtsi      | 220 ++++++++ >>  arch/arm/dts/imx8mn-var-som.dts              | 425 ++++++++++++++ >>  arch/arm/mach-imx/imx8m/Kconfig              |  9 + >>  board/variscite/imx8mn_var_som/Kconfig       | 17 + >>  board/variscite/imx8mn_var_som/Makefile      | 12 + >>  board/variscite/imx8mn_var_som/ddr4_timing.c | 529 ++++++++++++++++++ >>  .../variscite/imx8mn_var_som/imx8mn_var_som.c | 35 ++ >>  .../imx8mn_var_som/imximage-8mn-ddr4.cfg     | 12 + >>  board/variscite/imx8mn_var_som/spl.c         | 104 ++++ >>  configs/imx8mn_var_som_defconfig             | 98 ++++ >>  include/configs/imx8mn_var_som.h             | 106 ++++ >>  12 files changed, 1568 insertions(+) >>  create mode 100644 arch/arm/dts/imx8mn-var-som-u-boot.dtsi >>  create mode 100644 arch/arm/dts/imx8mn-var-som.dts >>  create mode 100644 board/variscite/imx8mn_var_som/Kconfig >>  create mode 100644 board/variscite/imx8mn_var_som/Makefile >>  create mode 100644 board/variscite/imx8mn_var_som/ddr4_timing.c >>  create mode 100644 board/variscite/imx8mn_var_som/imx8mn_var_som.c >>  create mode 100644 board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg >>  create mode 100644 board/variscite/imx8mn_var_som/spl.c >>  create mode 100644 configs/imx8mn_var_som_defconfig >>  create mode 100644 include/configs/imx8mn_var_som.h >> >> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile >> index cc34da7bd83..dfa034be80f 100644 >> --- a/arch/arm/dts/Makefile >> +++ b/arch/arm/dts/Makefile >> @@ -901,6 +901,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ >>         imx8mn-ddr4-evk.dtb \ >>         imx8mq-cm.dtb \ >>         imx8mn-evk.dtb \ >> +       imx8mn-var-som.dtb \ >>         imx8mq-evk.dtb \ >>         imx8mm-beacon-kit.dtb \ >>         imx8mn-beacon-kit.dtb \ >> diff --git a/arch/arm/dts/imx8mn-var-som-u-boot.dtsi b/arch/arm/dts/imx8mn-var-som-u-boot.dtsi >> new file mode 100644 >> index 00000000000..73df408bc82 >> --- /dev/null >> +++ b/arch/arm/dts/imx8mn-var-som-u-boot.dtsi >> @@ -0,0 +1,220 @@ >> +// SPDX-License-Identifier: GPL-2.0+ >> +/* >> + * Copyright 2021 Collabora Ltd. >> + */ >> + >> +/ { >> +       binman: binman { >> +               multiple-images; >> +       }; >> + >> +       wdt-reboot { >> +               compatible = "wdt-reboot"; >> +               wdt = <&wdog1>; >> +               u-boot,dm-spl; >> +       }; >> +}; >> + >> +&{/soc@0} { >> +       u-boot,dm-pre-reloc; >> +       u-boot,dm-spl; >> +}; >> + >> +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { >> +       u-boot,dm-spl; >> +}; >> + >> +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { >> +       u-boot,dm-spl; >> +}; >> + >> +&aips1 { >> +       u-boot,dm-spl; >> +       u-boot,dm-pre-reloc; > > You might want to consistently order properties alphabetically (e.g. see 3 nodes further up). Will do. > >> +}; >> + >> +&aips3 { >> +       u-boot,dm-spl; >> +}; >> + >> +&aips4 { >> +       u-boot,dm-spl; >> +}; >> + >> +&clk { >> +       u-boot,dm-spl; >> +       u-boot,dm-pre-reloc; > > Ditto. Will do. > >> +       /delete-property/ assigned-clocks; >> +       /delete-property/ assigned-clock-parents; >> +       /delete-property/ assigned-clock-rates; >> +}; >> + >> +&gpio1 { >> +       u-boot,dm-spl; >> +}; >> + >> +&gpio2 { >> +       u-boot,dm-spl; >> +}; >> + >> +&gpio4 { >> +       u-boot,dm-spl; >> +}; >> + >> +&i2c1 { >> +       u-boot,dm-spl; >> +}; >> + >> +&iomuxc { >> +       u-boot,dm-spl; >> +}; >> + >> +&osc_24m { >> +       u-boot,dm-spl; >> +       u-boot,dm-pre-reloc; > > Ditto. Will do. > >> +}; >> + >> +&pinctrl_i2c1 { >> +       u-boot,dm-spl; >> +}; >> + >> +&pinctrl_pmic { >> +       u-boot,dm-spl; >> +}; >> + >> +&pinctrl_reg_usdhc2_vmmc { >> +       u-boot,dm-spl; >> +}; >> + >> +&pinctrl_uart4 { >> +       u-boot,dm-spl; >> +}; >> + >> +&pinctrl_usdhc2 { >> +       u-boot,dm-spl; >> +}; >> + >> +&pinctrl_usdhc3 { >> +       u-boot,dm-spl; >> +}; >> + >> +&pinctrl_wdog { >> +       u-boot,dm-spl; >> +}; >> + >> +&uart4 { >> +       u-boot,dm-spl; >> +}; >> + >> +&usdhc2 { >> +       u-boot,dm-spl; >> +}; >> + >> +&usdhc3 { >> +       u-boot,dm-spl; >> +}; >> + >> +&wdog1 { >> +       u-boot,dm-spl; >> +}; >> + >> +&binman { >> +       u-boot-spl-ddr { >> +               filename = "u-boot-spl-ddr.bin"; >> +               pad-byte = <0xff>; >> +               align-size = <4>; >> +               align = <4>; >> + >> +               u-boot-spl { >> +                       align-end = <4>; >> +               }; >> + >> +               blob_1: blob-ext@1 { >> +                       filename = "ddr4_imem_1d.bin"; >> +                       size = <0x8000>; >> +               }; >> + >> +               blob_2: blob-ext@2 { >> +                       filename = "ddr4_dmem_1d.bin"; >> +                       size = <0x4000>; >> +               }; >> + >> +               blob_3: blob-ext@3 { >> +                       filename = "ddr4_imem_2d.bin"; >> +                       size = <0x8000>; >> +               }; >> + >> +               blob_4: blob-ext@4 { >> +                       filename = "ddr4_dmem_2d.bin"; >> +                       size = <0x4000>; >> +               }; >> +       }; >> + >> +       itb { >> +               filename = "u-boot.itb"; >> + >> +               fit { >> +                       description = "Configuration to load ATF before U-Boot"; >> +                       #address-cells = <1>; >> +                       fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; >> + >> +                       images { >> +                               uboot { >> +                                       description = "U-Boot (64-bit)"; >> +                                       type = "standalone"; >> +                                       arch = "arm64"; >> +                                       compression = "none"; >> +                                       load = <CONFIG_SYS_TEXT_BASE>; >> + >> +                                       uboot_blob: blob-ext { >> +                                               filename = "u-boot-nodtb.bin"; >> +                                       }; >> +                               }; >> + >> +                               atf { >> +                                       description = "ARM Trusted Firmware"; >> +                                       type = "firmware"; >> +                                       arch = "arm64"; >> +                                       compression = "none"; >> +                                       load = <0x960000>; >> +                                       entry = <0x960000>; >> + >> +                                       atf_blob: blob-ext { >> +                                               filename = "bl31.bin"; >> +                                       }; >> +                               }; >> + >> +                               fdt { >> +                                       description = "NAME"; >> +                                       type = "flat_dt"; >> +                                       compression = "none"; >> + >> +                                       uboot_fdt_blob: blob-ext { >> +                                               filename = "u-boot.dtb"; >> +                                       }; >> +                               }; >> +                       }; >> + >> +                       configurations { >> +                               default = "conf"; >> + >> +                               conf { >> +                                       description = "NAME"; >> +                                       firmware = "uboot"; >> +                                       loadables = "atf"; >> +                                       fdt = "fdt"; >> +                               }; >> +                       }; >> +               }; >> +       }; >> + >> +       flash { >> +               mkimage { >> +                       args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000"; >> + >> +                       blob { >> +                               filename = "u-boot-spl-ddr.bin"; >> +                       }; >> +               }; >> +       }; >> +}; > > I guess that binman configuration could be unified and further cleaned-up on the Nanos just like what is in- > flight for the Mini [1]. Thanks for the reference. If you're okay with it, I could submit a follow up patchset with the unification later on. > >> diff --git a/arch/arm/dts/imx8mn-var-som.dts b/arch/arm/dts/imx8mn-var-som.dts >> new file mode 100644 >> index 00000000000..e094d25af8c >> --- /dev/null >> +++ b/arch/arm/dts/imx8mn-var-som.dts >> @@ -0,0 +1,425 @@ >> +// SPDX-License-Identifier: GPL-2.0+ >> +/* >> + * Copyright 2021 Collabora Ltd. >> + */ >> + >> +/dts-v1/; >> + >> +#include "imx8mn.dtsi" >> + >> +/ { >> +       model = "Variscite VAR-SOM-MX8MN module"; >> +       compatible = "variscite,var-som-mx8mn", "fsl,imx8mn"; >> + >> +       chosen { >> +               bootargs = "console=ttymxc3,115200 earlycon=ec_imx6q,0x30a60000,115200"; > > I believe that earlycon stuff after the equal sign is some downstream stuff which may even prohibit any kind of > mainline from successfully being run. You're right, will remove in v2. > >> +               stdout-path = &uart4; >> +       }; >> + >> +       reg_usdhc2_vmmc: regulator-usdhc2-vmmc { >> +               compatible = "regulator-fixed"; >> +               pinctrl-names = "default"; >> +               pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; >> +               regulator-name = "VSD_3V3"; >> +               regulator-min-microvolt = <3300000>; >> +               regulator-max-microvolt = <3300000>; >> +               gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; >> +               enable-active-high; >> +       }; >> + >> +       reg_eth_phy: regulator-eth-phy { >> +               compatible = "regulator-fixed"; >> +               pinctrl-names = "default"; >> +               pinctrl-0 = <&pinctrl_reg_eth_phy>; >> +               regulator-name = "eth_phy_pwr"; >> +               regulator-min-microvolt = <3300000>; >> +               regulator-max-microvolt = <3300000>; >> +               gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; >> +               enable-active-high; >> +       }; >> +}; >> + >> +&A53_0 { >> +       cpu-supply = <&buck2_reg>; >> +}; >> + >> +&A53_1 { >> +       cpu-supply = <&buck2_reg>; >> +}; >> + >> +&A53_2 { >> +       cpu-supply = <&buck2_reg>; >> +}; >> + >> +&A53_3 { >> +       cpu-supply = <&buck2_reg>; >> +}; >> + >> +&fec1 { >> +       pinctrl-names = "default"; >> +       pinctrl-0 = <&pinctrl_fec1>; >> +       phy-mode = "rgmii"; > > I assume you do want the MAC to explicitly add RX and TX delays, right? Indeed, RX and TX delays are provided by the MAC, not PHY, in this case. > >> +       phy-handle = <ðphy>; >> +       phy-supply = <®_eth_phy>; >> +       phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; >> +       phy-reset-duration = <10>; >> +       fsl,magic-packet; >> +       status = "okay"; >> + >> +       mdio { >> +               #address-cells = <1>; >> +               #size-cells = <0>; >> + >> +               ethphy: ethernet-phy@4 { >> +                       compatible = "ethernet-phy-ieee802.3-c22"; >> +                       reg = <4>; >> +               }; >> +       }; >> +}; >> + >> +&i2c1 { >> +       clock-frequency = <400000>; >> +       pinctrl-names = "default"; >> +       pinctrl-0 = <&pinctrl_i2c1>; >> +       status = "okay"; >> + >> +       pmic@4b { >> +               compatible = "rohm,bd71847"; >> +               reg = <0x4b>; >> +               pinctrl-names = "default"; >> +               pinctrl-0 = <&pinctrl_pmic>; >> +               interrupt-parent = <&gpio2>; >> +               interrupts = <8 IRQ_TYPE_LEVEL_LOW>; >> +               rohm,reset-snvs-powered; >> + >> +               regulators { >> +                       buck1_reg: BUCK1 { >> +                               regulator-name = "buck1"; >> +                               regulator-min-microvolt = <700000>; >> +                               regulator-max-microvolt = <1300000>; >> +                               regulator-boot-on; >> +                               regulator-always-on; >> +                               regulator-ramp-delay = <1250>; >> +                       }; >> + >> +                       buck2_reg: BUCK2 { >> +                               regulator-name = "buck2"; >> +                               regulator-min-microvolt = <700000>; >> +                               regulator-max-microvolt = <1300000>; >> +                               regulator-boot-on; >> +                               regulator-always-on; >> +                               regulator-ramp-delay = <1250>; >> +                               rohm,dvs-run-voltage = <1000000>; >> +                               rohm,dvs-idle-voltage = <900000>; >> +                       }; >> + >> +                       buck3_reg: BUCK3 { >> +                               regulator-name = "buck3"; >> +                               regulator-min-microvolt = <700000>; >> +                               regulator-max-microvolt = <1350000>; >> +                               regulator-boot-on; >> +                               regulator-always-on; >> +                       }; >> + >> +                       buck4_reg: BUCK4 { >> +                               regulator-name = "buck4"; >> +                               regulator-min-microvolt = <2600000>; >> +                               regulator-max-microvolt = <3300000>; >> +                               regulator-boot-on; >> +                               regulator-always-on; >> +                       }; >> + >> +                       buck5_reg: BUCK5 { >> +                               regulator-name = "buck5"; >> +                               regulator-min-microvolt = <1605000>; >> +                               regulator-max-microvolt = <1995000>; >> +                               regulator-boot-on; >> +                               regulator-always-on; >> +                       }; >> + >> +                       buck6_reg: BUCK6 { >> +                               regulator-name = "buck6"; >> +                               regulator-min-microvolt = <800000>; >> +                               regulator-max-microvolt = <1400000>; >> +                               regulator-boot-on; >> +                               regulator-always-on; >> +                       }; >> + >> +                       ldo1_reg: LDO1 { >> +                               regulator-name = "ldo1"; >> +                               regulator-min-microvolt = <1600000>; >> +                               regulator-max-microvolt = <1900000>; >> +                               regulator-boot-on; >> +                               regulator-always-on; >> +                       }; >> + >> +                       ldo2_reg: LDO2 { >> +                               regulator-name = "ldo2"; >> +                               regulator-min-microvolt = <800000>; >> +                               regulator-max-microvolt = <900000>; >> +                               regulator-boot-on; >> +                               regulator-always-on; >> +                       }; >> + >> +                       ldo3_reg: LDO3 { >> +                               regulator-name = "ldo3"; >> +                               regulator-min-microvolt = <1800000>; >> +                               regulator-max-microvolt = <3300000>; >> +                               regulator-boot-on; >> +                               regulator-always-on; >> +                       }; >> + >> +                       ldo4_reg: LDO4 { >> +                               regulator-name = "ldo4"; >> +                               regulator-min-microvolt = <900000>; >> +                               regulator-max-microvolt = <1800000>; >> +                               regulator-always-on; >> +                       }; >> + >> +                       ldo5_reg: LDO5 { >> +                               regulator-name = "ldo5"; >> +                               regulator-min-microvolt = <1800000>; >> +                               regulator-max-microvolt = <1800000>; >> +                               regulator-always-on; >> +                       }; >> + >> +                       ldo6_reg: LDO6 { >> +                               regulator-name = "ldo6"; >> +                               regulator-min-microvolt = <900000>; >> +                               regulator-max-microvolt = <1800000>; >> +                               regulator-boot-on; >> +                               regulator-always-on; >> +                       }; >> +               }; >> +       }; >> +}; >> + >> +/* Console */ >> +&uart4 { >> +       pinctrl-names = "default"; >> +       pinctrl-0 = <&pinctrl_uart4>; >> +       status = "okay"; >> +}; >> + >> +&usbotg1 { >> +       dr_mode = "peripheral"; >> +       status = "okay"; >> +}; >> + >> +/* SD */ >> +&usdhc2 { >> +       assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; >> +       assigned-clock-rates = <200000000>; >> +       pinctrl-names = "default", "state_100mhz", "state_200mhz"; >> +       pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; >> +       pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; >> +       pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; >> +       cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; >> +       bus-width = <4>; >> +       vmmc-supply = <®_usdhc2_vmmc>; >> +       status = "okay"; >> +}; >> + >> +/* eMMC */ >> +&usdhc3 { >> +       assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; >> +       assigned-clock-rates = <400000000>; >> +       pinctrl-names = "default", "state_100mhz", "state_200mhz"; >> +       pinctrl-0 = <&pinctrl_usdhc3>; >> +       pinctrl-1 = <&pinctrl_usdhc3_100mhz>; >> +       pinctrl-2 = <&pinctrl_usdhc3_200mhz>; >> +       bus-width = <8>; >> +       non-removable; >> +       status = "okay"; >> +}; >> + >> +&wdog1 { >> +       pinctrl-names = "default"; >> +       pinctrl-0 = <&pinctrl_wdog>; >> +       fsl,ext-reset-output; >> +       status = "okay"; >> +}; >> + >> +&iomuxc { >> +       pinctrl_fec1: fec1grp { >> +               fsl,pins = < >> +                       MX8MN_IOMUXC_ENET_MDC_ENET1_MDC                 0x3 >> +                       MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO               0x3 >> +                       MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f >> +                       MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f >> +                       MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f >> +                       MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f >> +                       MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91 >> +                       MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91 >> +                       MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91 >> +                       MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91 >> +                       MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f >> +                       MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91 >> +                       MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91 >> +                       MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f >> +                       MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9               0x19 >> +               >; >> +       }; >> + >> +       pinctrl_i2c1: i2c1grp { >> +               fsl,pins = < >> +                       MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3 >> +                       MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3 >> +               >; >> +       }; >> + >> +       pinctrl_pmic: pmicirqgrp { >> +               fsl,pins = < >> +                       MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8        0x141 >> +               >; >> +       }; >> + >> +       pinctrl_reg_eth_phy: regethphygrp { >> +               fsl,pins = < >> +                       MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9        0x41 >> +               >; >> +       }; >> + >> + >> +       pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { >> +               fsl,pins = < >> +                       MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22       0x41 >> +               >; >> +       }; >> + >> +       pinctrl_uart4: uart4grp { >> +               fsl,pins = < >> +                       MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX     0x140 >> +                       MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX     0x140 >> +               >; >> +       }; >> + >> +       pinctrl_usdhc1: usdhc1grp { >> +               fsl,pins = < >> +                       MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK         0x190 >> +                       MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d0 >> +                       MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d0 >> +                       MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d0 >> +                       MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d0 >> +                       MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d0 >> +               >; >> +       }; >> + >> +       pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { >> +               fsl,pins = < >> +                       MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK         0x194 >> +                       MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d4 >> +                       MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d4 >> +                       MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d4 >> +                       MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d4 >> +                       MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d4 >> +               >; >> +       }; >> + >> +       pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { >> +               fsl,pins = < >> +                       MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK         0x196 >> +                       MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d6 >> +                       MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d6 >> +                       MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d6 >> +                       MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d6 >> +                       MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d6 >> +               >; >> +       }; >> + >> +       pinctrl_usdhc2_gpio: usdhc2gpiogrp { >> +               fsl,pins = < >> +                       MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10      0x41 >> +               >; >> +       }; >> + >> +       pinctrl_usdhc2: usdhc2grp { >> +               fsl,pins = < >> +                       MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x190 >> +                       MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0 >> +                       MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0 >> +                       MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0 >> +                       MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0 >> +                       MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0 >> +                       MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0 >> +               >; >> +       }; >> + >> +       pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { >> +               fsl,pins = < >> +                       MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x194 >> +                       MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4 >> +                       MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4 >> +                       MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4 >> +                       MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4 >> +                       MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4 >> +                       MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0 >> +               >; >> +       }; >> + >> +       pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { >> +               fsl,pins = < >> +                       MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x196 >> +                       MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6 >> +                       MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6 >> +                       MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6 >> +                       MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6 >> +                       MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6 >> +                       MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0 >> +               >; >> +       }; >> + >> +       pinctrl_usdhc3: usdhc3grp { >> +               fsl,pins = < >> +                       MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK       0x190 >> +                       MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d0 >> +                       MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d0 >> +                       MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d0 >> +                       MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d0 >> +                       MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d0 >> +                       MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d0 >> +                       MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d0 >> +                       MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d0 >> +                       MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d0 >> +                       MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x190 >> +               >; >> +       }; >> + >> +       pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { >> +               fsl,pins = < >> +                       MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK       0x194 >> +                       MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d4 >> +                       MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d4 >> +                       MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d4 >> +                       MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d4 >> +                       MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d4 >> +                       MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d4 >> +                       MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d4 >> +                       MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d4 >> +                       MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d4 >> +                       MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x194 >> +               >; >> +       }; >> + >> +       pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { >> +               fsl,pins = < >> +                       MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK       0x196 >> +                       MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d6 >> +                       MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d6 >> +                       MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d6 >> +                       MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d6 >> +                       MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d6 >> +                       MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d6 >> +                       MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d6 >> +                       MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d6 >> +                       MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d6 >> +                       MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x196 >> +               >; >> +       }; >> + >> +       pinctrl_wdog: wdoggrp { >> +               fsl,pins = < >> +                       MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B    0x166 >> +               >; >> +       }; >> +}; >> diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig >> index 276b8bd9742..82a5ab8ad00 100644 >> --- a/arch/arm/mach-imx/imx8m/Kconfig >> +++ b/arch/arm/mach-imx/imx8m/Kconfig >> @@ -108,6 +108,14 @@ config TARGET_PICO_IMX8MQ >>         select IMX8MQ >>         select IMX8M_LPDDR4 >>  >> +config TARGET_IMX8MN_VAR_SOM >> +       bool "imx8mn_var_som" >> +       select BINMAN >> +       select IMX8MN >> +       select SUPPORT_SPL >> +       select IMX8M_DDR4 >> +       select IMX8M_BOARD_INIT_DRAM >> + >>  config TARGET_VERDIN_IMX8MM >>         bool "Support Toradex Verdin iMX8M Mini module" >>         select BINMAN >> @@ -171,6 +179,7 @@ source "board/phytec/phycore_imx8mm/Kconfig" >>  source "board/phytec/phycore_imx8mp/Kconfig" >>  source "board/ronetix/imx8mq-cm/Kconfig" >>  source "board/technexion/pico-imx8mq/Kconfig" >> +source "board/variscite/imx8mn_var_som/Kconfig" >>  source "board/toradex/verdin-imx8mm/Kconfig" >>  >>  endif >> diff --git a/board/variscite/imx8mn_var_som/Kconfig b/board/variscite/imx8mn_var_som/Kconfig >> new file mode 100644 >> index 00000000000..cfe6fc8c2c7 >> --- /dev/null >> +++ b/board/variscite/imx8mn_var_som/Kconfig >> @@ -0,0 +1,17 @@ >> +if TARGET_IMX8MN_VAR_SOM >> + >> +config SYS_BOARD >> +       default "imx8mn_var_som" >> + >> +config SYS_VENDOR >> +       default "variscite" >> + >> +config SYS_CONFIG_NAME >> +       default "imx8mn_var_som" >> + >> +config IMX_CONFIG >> +       default "board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg" >> + >> +source "board/freescale/common/Kconfig" >> + >> +endif >> diff --git a/board/variscite/imx8mn_var_som/Makefile b/board/variscite/imx8mn_var_som/Makefile >> new file mode 100644 >> index 00000000000..a8b6a343ffc >> --- /dev/null >> +++ b/board/variscite/imx8mn_var_som/Makefile >> @@ -0,0 +1,12 @@ >> +# >> +# Copyright 2021 Collabora Ltd. >> +# >> +# SPDX-License-Identifier:     GPL-2.0+ >> +# >> + >> +obj-y += imx8mn_var_som.o >> + >> +ifdef CONFIG_SPL_BUILD >> +obj-y += spl.o >> +obj-y += ddr4_timing.o >> +endif >> diff --git a/board/variscite/imx8mn_var_som/ddr4_timing.c b/board/variscite/imx8mn_var_som/ddr4_timing.c >> new file mode 100644 >> index 00000000000..6d3d1805c89 >> --- /dev/null >> +++ b/board/variscite/imx8mn_var_som/ddr4_timing.c >> @@ -0,0 +1,529 @@ >> +/* >> + * Copyright 2019 NXP >> + * >> + * SPDX-License-Identifier:    GPL-2.0+ >> + * >> + * Generated code from MX8M_DDR_tool >> + * Align with uboot version: >> + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga >> + */ >> + >> +#include <linux/kernel.h> >> +#include <asm/arch/ddr.h> >> + >> +static struct dram_cfg_param ddr_ddrc_cfg[] = { >> +       /** Initialize DDRC registers **/ >> +       { 0x3d400000, 0x81040010 }, >> +       { 0x3d400030, 0x20 }, >> +       { 0x3d400034, 0x221306 }, >> +       { 0x3d400050, 0x210070 }, >> +       { 0x3d400054, 0x10008 }, >> +       { 0x3d400060, 0x0 }, >> +       { 0x3d400064, 0x9200d2 }, >> +       { 0x3d4000c0, 0x0 }, >> +       { 0x3d4000c4, 0x1000 }, >> +       { 0x3d4000d0, 0xc0030126 }, >> +       { 0x3d4000d4, 0x770000 }, >> +       { 0x3d4000dc, 0x8340105 }, >> +       { 0x3d4000e0, 0x180200 }, >> +       { 0x3d4000e4, 0x110000 }, >> +       { 0x3d4000e8, 0x2000600 }, >> +       { 0x3d4000ec, 0x810 }, >> +       { 0x3d4000f0, 0x20 }, >> +       { 0x3d4000f4, 0xec7 }, >> +       { 0x3d400100, 0x11122914 }, >> +       { 0x3d400104, 0x4051c }, >> +       { 0x3d400108, 0x608050d }, >> +       { 0x3d40010c, 0x400c }, >> +       { 0x3d400110, 0x8030409 }, >> +       { 0x3d400114, 0x6060403 }, >> +       { 0x3d40011c, 0x606 }, >> +       { 0x3d400120, 0x5050d08 }, >> +       { 0x3d400124, 0x2040a }, >> +       { 0x3d40012c, 0x1409010e }, >> +       { 0x3d400130, 0x8 }, >> +       { 0x3d40013c, 0x0 }, >> +       { 0x3d400180, 0x1000040 }, >> +       { 0x3d400184, 0x493e }, >> +       { 0x3d400190, 0x38b8207 }, >> +       { 0x3d400194, 0x2020303 }, >> +       { 0x3d400198, 0x7f04011 }, >> +       { 0x3d40019c, 0xb0 }, >> +       { 0x3d4001a0, 0xe0400018 }, >> +       { 0x3d4001a4, 0x48005a }, >> +       { 0x3d4001a8, 0x80000000 }, >> +       { 0x3d4001b0, 0x1 }, >> +       { 0x3d4001b4, 0xb07 }, >> +       { 0x3d4001b8, 0x4 }, >> +       { 0x3d4001c0, 0x1 }, >> +       { 0x3d4001c4, 0x0 }, >> +       { 0x3d400200, 0x3f1f }, >> +       { 0x3d400204, 0x3f0909 }, >> +       { 0x3d400208, 0x700 }, >> +       { 0x3d40020c, 0x0 }, >> +       { 0x3d400210, 0x1f1f }, >> +       { 0x3d400214, 0x7070707 }, >> +       { 0x3d400218, 0x7070707 }, >> +       { 0x3d40021c, 0xf0f }, >> +       { 0x3d400220, 0x3f01 }, >> +       { 0x3d400240, 0x6000610 }, >> +       { 0x3d400244, 0x1323 }, >> +       { 0x3d400400, 0x100 }, >> +       { 0x3d400250, 0x317d1a07 }, >> +       { 0x3d400254, 0xf }, >> +       { 0x3d40025c, 0x2a001b76 }, >> +       { 0x3d400264, 0x7300b473 }, >> +       { 0x3d40026c, 0x30000e06 }, >> +       { 0x3d400300, 0x14 }, >> +       { 0x3d40036c, 0x10 }, >> +       { 0x3d400404, 0x13193 }, >> +       { 0x3d400408, 0x6096 }, >> +       { 0x3d400490, 0x1 }, >> +       { 0x3d400494, 0x2000c00 }, >> +       { 0x3d400498, 0x3c00db }, >> +       { 0x3d40049c, 0x100009 }, >> +       { 0x3d4004a0, 0x2 }, >> +       { 0x3d402050, 0x210070 }, >> +       { 0x3d402064, 0x40005e }, >> +       { 0x3d4020dc, 0x40105 }, >> +       { 0x3d4020e0, 0x0 }, >> +       { 0x3d4020e8, 0x2000600 }, >> +       { 0x3d4020ec, 0x10 }, >> +       { 0x3d402100, 0xb081209 }, >> +       { 0x3d402104, 0x2020d }, >> +       { 0x3d402108, 0x5050309 }, >> +       { 0x3d40210c, 0x400c }, >> +       { 0x3d402110, 0x5030206 }, >> +       { 0x3d402114, 0x3030202 }, >> +       { 0x3d40211c, 0x303 }, >> +       { 0x3d402120, 0x3030d04 }, >> +       { 0x3d402124, 0x20208 }, >> +       { 0x3d40212c, 0x1005010e }, >> +       { 0x3d402130, 0x8 }, >> +       { 0x3d40213c, 0x0 }, >> +       { 0x3d402180, 0x1000040 }, >> +       { 0x3d402190, 0x3858204 }, >> +       { 0x3d402194, 0x2020303 }, >> +       { 0x3d4021b4, 0x504 }, >> +       { 0x3d4021b8, 0x4 }, >> +       { 0x3d402240, 0x6000604 }, >> +       { 0x3d4020f4, 0xec7 }, >> +}; >> + >> +/* PHY Initialize Configuration */ >> +static struct dram_cfg_param ddr_ddrphy_cfg[] = { >> +       { 0x1005f, 0x2fd }, >> +       { 0x1015f, 0x2fd }, >> +       { 0x1105f, 0x2fd }, >> +       { 0x1115f, 0x2fd }, >> +       { 0x11005f, 0x2fd }, >> +       { 0x11015f, 0x2fd }, >> +       { 0x11105f, 0x2fd }, >> +       { 0x11115f, 0x2fd }, >> +       { 0x55, 0x355 }, >> +       { 0x1055, 0x355 }, >> +       { 0x2055, 0x355 }, >> +       { 0x3055, 0x355 }, >> +       { 0x4055, 0x55 }, >> +       { 0x5055, 0x55 }, >> +       { 0x6055, 0x355 }, >> +       { 0x7055, 0x355 }, >> +       { 0x8055, 0x355 }, >> +       { 0x9055, 0x355 }, >> +       { 0x200c5, 0xa }, >> +       { 0x1200c5, 0x6 }, >> +       { 0x2002e, 0x2 }, >> +       { 0x12002e, 0x1 }, >> +       { 0x20024, 0x8 }, >> +       { 0x2003a, 0x2 }, >> +       { 0x120024, 0x8 }, >> +       { 0x2003a, 0x2 }, >> +       { 0x20056, 0x6 }, >> +       { 0x120056, 0xa }, >> +       { 0x1004d, 0x1a }, >> +       { 0x1014d, 0x1a }, >> +       { 0x1104d, 0x1a }, >> +       { 0x1114d, 0x1a }, >> +       { 0x11004d, 0x1a }, >> +       { 0x11014d, 0x1a }, >> +       { 0x11104d, 0x1a }, >> +       { 0x11114d, 0x1a }, >> +       { 0x10049, 0xe38 }, >> +       { 0x10149, 0xe38 }, >> +       { 0x11049, 0xe38 }, >> +       { 0x11149, 0xe38 }, >> +       { 0x110049, 0xe38 }, >> +       { 0x110149, 0xe38 }, >> +       { 0x111049, 0xe38 }, >> +       { 0x111149, 0xe38 }, >> +       { 0x43, 0x63 }, >> +       { 0x1043, 0x63 }, >> +       { 0x2043, 0x63 }, >> +       { 0x3043, 0x63 }, >> +       { 0x4043, 0x63 }, >> +       { 0x5043, 0x63 }, >> +       { 0x6043, 0x63 }, >> +       { 0x7043, 0x63 }, >> +       { 0x8043, 0x63 }, >> +       { 0x9043, 0x63 }, >> +       { 0x20018, 0x1 }, >> +       { 0x20075, 0x2 }, >> +       { 0x20050, 0x0 }, >> +       { 0x20008, 0x258 }, >> +       { 0x120008, 0x10a }, >> +       { 0x20088, 0x9 }, >> +       { 0x200b2, 0x268 }, >> +       { 0x10043, 0x5b1 }, >> +       { 0x10143, 0x5b1 }, >> +       { 0x11043, 0x5b1 }, >> +       { 0x11143, 0x5b1 }, >> +       { 0x1200b2, 0x268 }, >> +       { 0x110043, 0x5b1 }, >> +       { 0x110143, 0x5b1 }, >> +       { 0x111043, 0x5b1 }, >> +       { 0x111143, 0x5b1 }, >> +       { 0x200fa, 0x1 }, >> +       { 0x1200fa, 0x1 }, >> +       { 0x20019, 0x5 }, >> +       { 0x120019, 0x5 }, >> +       { 0x200f0, 0x5555 }, >> +       { 0x200f1, 0x5555 }, >> +       { 0x200f2, 0x5555 }, >> +       { 0x200f3, 0x5555 }, >> +       { 0x200f4, 0x5555 }, >> +       { 0x200f5, 0x5555 }, >> +       { 0x200f6, 0x5555 }, >> +       { 0x200f7, 0xf000 }, >> +       { 0x20025, 0x0 }, >> +       { 0x2002d, 0x0 }, >> +       { 0x12002d, 0x0 }, >> +       { 0x2005b, 0x7529 }, >> +       { 0x2005c, 0x0 }, >> +       { 0x200c7, 0x21 }, >> +       { 0x200ca, 0x24 }, >> +       { 0x200cc, 0x1f7 }, >> +       { 0x1200c7, 0x21 }, >> +       { 0x1200ca, 0x24 }, >> +       { 0x1200cc, 0x1f7 }, >> +       { 0x2007d, 0x212 }, >> +       { 0x12007d, 0x212 }, >> +       { 0x2007c, 0x61 }, >> +       { 0x12007c, 0x61 }, >> +       { 0x1004a, 0x500 }, >> +       { 0x1104a, 0x500 }, >> +       { 0x2002c, 0x0 }, >> +}; >> + >> +/* P0 message block parameter for training firmware */ >> +static struct dram_cfg_param ddr_fsp0_cfg[] = { >> +       { 0xd0000, 0x0 }, >> +       { 0x54003, 0x960 }, >> +       { 0x54004, 0x2 }, >> +       { 0x54005, 0x2830 }, >> +       { 0x54006, 0x25e }, >> +       { 0x54007, 0x1000 }, >> +       { 0x54008, 0x101 }, >> +       { 0x5400b, 0x31f }, >> +       { 0x5400c, 0xc8 }, >> +       { 0x5400d, 0x100 }, >> +       { 0x54012, 0x1 }, >> +       { 0x5402f, 0x834 }, >> +       { 0x54030, 0x105 }, >> +       { 0x54031, 0x18 }, >> +       { 0x54032, 0x200 }, >> +       { 0x54033, 0x200 }, >> +       { 0x54034, 0x600 }, >> +       { 0x54035, 0x810 }, >> +       { 0x54036, 0x101 }, >> +       { 0x5403f, 0x1221 }, >> +       { 0x541fc, 0x100 }, >> +       { 0xd0000, 0x1 }, >> +}; >> + >> +/* P1 message block parameter for training firmware */ >> +static struct dram_cfg_param ddr_fsp1_cfg[] = { >> +       { 0xd0000, 0x0 }, >> +       { 0x54002, 0x1 }, >> +       { 0x54003, 0x42a }, >> +       { 0x54004, 0x2 }, >> +       { 0x54005, 0x2830 }, >> +       { 0x54006, 0x25e }, >> +       { 0x54007, 0x1000 }, >> +       { 0x54008, 0x101 }, >> +       { 0x5400b, 0x21f }, >> +       { 0x5400c, 0xc8 }, >> +       { 0x5400d, 0x100 }, >> +       { 0x54012, 0x1 }, >> +       { 0x5402f, 0x4 }, >> +       { 0x54030, 0x105 }, >> +       { 0x54033, 0x200 }, >> +       { 0x54034, 0x600 }, >> +       { 0x54035, 0x10 }, >> +       { 0x54036, 0x101 }, >> +       { 0x5403f, 0x1221 }, >> +       { 0x541fc, 0x100 }, >> +       { 0xd0000, 0x1 }, >> +}; >> + >> +/* P0 2D message block parameter for training firmware */ >> +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { >> +       { 0xd0000, 0x0 }, >> +       { 0x54003, 0x960 }, >> +       { 0x54004, 0x2 }, >> +       { 0x54005, 0x2830 }, >> +       { 0x54006, 0x25e }, >> +       { 0x54007, 0x1000 }, >> +       { 0x54008, 0x101 }, >> +       { 0x5400b, 0x61 }, >> +       { 0x5400c, 0xc8 }, >> +       { 0x5400d, 0x100 }, >> +       { 0x5400e, 0x1f7f }, >> +       { 0x54012, 0x1 }, >> +       { 0x5402f, 0x834 }, >> +       { 0x54030, 0x105 }, >> +       { 0x54031, 0x18 }, >> +       { 0x54032, 0x200 }, >> +       { 0x54033, 0x200 }, >> +       { 0x54034, 0x600 }, >> +       { 0x54035, 0x810 }, >> +       { 0x54036, 0x101 }, >> +       { 0x5403f, 0x1221 }, >> +       { 0x541fc, 0x100 }, >> +       { 0xd0000, 0x1 }, >> +}; >> + >> +/* DRAM PHY init engine image */ >> +static struct dram_cfg_param ddr_phy_pie[] = { >> +       { 0xd0000, 0x0 }, >> +       { 0x90000, 0x10 }, >> +       { 0x90001, 0x400 }, >> +       { 0x90002, 0x10e }, >> +       { 0x90003, 0x0 }, >> +       { 0x90004, 0x0 }, >> +       { 0x90005, 0x8 }, >> +       { 0x90029, 0xb }, >> +       { 0x9002a, 0x480 }, >> +       { 0x9002b, 0x109 }, >> +       { 0x9002c, 0x8 }, >> +       { 0x9002d, 0x448 }, >> +       { 0x9002e, 0x139 }, >> +       { 0x9002f, 0x8 }, >> +       { 0x90030, 0x478 }, >> +       { 0x90031, 0x109 }, >> +       { 0x90032, 0x2 }, >> +       { 0x90033, 0x10 }, >> +       { 0x90034, 0x139 }, >> +       { 0x90035, 0xb }, >> +       { 0x90036, 0x7c0 }, >> +       { 0x90037, 0x139 }, >> +       { 0x90038, 0x44 }, >> +       { 0x90039, 0x633 }, >> +       { 0x9003a, 0x159 }, >> +       { 0x9003b, 0x14f }, >> +       { 0x9003c, 0x630 }, >> +       { 0x9003d, 0x159 }, >> +       { 0x9003e, 0x47 }, >> +       { 0x9003f, 0x633 }, >> +       { 0x90040, 0x149 }, >> +       { 0x90041, 0x4f }, >> +       { 0x90042, 0x633 }, >> +       { 0x90043, 0x179 }, >> +       { 0x90044, 0x8 }, >> +       { 0x90045, 0xe0 }, >> +       { 0x90046, 0x109 }, >> +       { 0x90047, 0x0 }, >> +       { 0x90048, 0x7c8 }, >> +       { 0x90049, 0x109 }, >> +       { 0x9004a, 0x0 }, >> +       { 0x9004b, 0x1 }, >> +       { 0x9004c, 0x8 }, >> +       { 0x9004d, 0x0 }, >> +       { 0x9004e, 0x45a }, >> +       { 0x9004f, 0x9 }, >> +       { 0x90050, 0x0 }, >> +       { 0x90051, 0x448 }, >> +       { 0x90052, 0x109 }, >> +       { 0x90053, 0x40 }, >> +       { 0x90054, 0x633 }, >> +       { 0x90055, 0x179 }, >> +       { 0x90056, 0x1 }, >> +       { 0x90057, 0x618 }, >> +       { 0x90058, 0x109 }, >> +       { 0x90059, 0x40c0 }, >> +       { 0x9005a, 0x633 }, >> +       { 0x9005b, 0x149 }, >> +       { 0x9005c, 0x8 }, >> +       { 0x9005d, 0x4 }, >> +       { 0x9005e, 0x48 }, >> +       { 0x9005f, 0x4040 }, >> +       { 0x90060, 0x633 }, >> +       { 0x90061, 0x149 }, >> +       { 0x90062, 0x0 }, >> +       { 0x90063, 0x4 }, >> +       { 0x90064, 0x48 }, >> +       { 0x90065, 0x40 }, >> +       { 0x90066, 0x633 }, >> +       { 0x90067, 0x149 }, >> +       { 0x90068, 0x10 }, >> +       { 0x90069, 0x4 }, >> +       { 0x9006a, 0x18 }, >> +       { 0x9006b, 0x0 }, >> +       { 0x9006c, 0x4 }, >> +       { 0x9006d, 0x78 }, >> +       { 0x9006e, 0x549 }, >> +       { 0x9006f, 0x633 }, >> +       { 0x90070, 0x159 }, >> +       { 0x90071, 0xd49 }, >> +       { 0x90072, 0x633 }, >> +       { 0x90073, 0x159 }, >> +       { 0x90074, 0x94a }, >> +       { 0x90075, 0x633 }, >> +       { 0x90076, 0x159 }, >> +       { 0x90077, 0x441 }, >> +       { 0x90078, 0x633 }, >> +       { 0x90079, 0x149 }, >> +       { 0x9007a, 0x42 }, >> +       { 0x9007b, 0x633 }, >> +       { 0x9007c, 0x149 }, >> +       { 0x9007d, 0x1 }, >> +       { 0x9007e, 0x633 }, >> +       { 0x9007f, 0x149 }, >> +       { 0x90080, 0x0 }, >> +       { 0x90081, 0xe0 }, >> +       { 0x90082, 0x109 }, >> +       { 0x90083, 0xa }, >> +       { 0x90084, 0x10 }, >> +       { 0x90085, 0x109 }, >> +       { 0x90086, 0x9 }, >> +       { 0x90087, 0x3c0 }, >> +       { 0x90088, 0x149 }, >> +       { 0x90089, 0x9 }, >> +       { 0x9008a, 0x3c0 }, >> +       { 0x9008b, 0x159 }, >> +       { 0x9008c, 0x18 }, >> +       { 0x9008d, 0x10 }, >> +       { 0x9008e, 0x109 }, >> +       { 0x9008f, 0x0 }, >> +       { 0x90090, 0x3c0 }, >> +       { 0x90091, 0x109 }, >> +       { 0x90092, 0x18 }, >> +       { 0x90093, 0x4 }, >> +       { 0x90094, 0x48 }, >> +       { 0x90095, 0x18 }, >> +       { 0x90096, 0x4 }, >> +       { 0x90097, 0x58 }, >> +       { 0x90098, 0xb }, >> +       { 0x90099, 0x10 }, >> +       { 0x9009a, 0x109 }, >> +       { 0x9009b, 0x1 }, >> +       { 0x9009c, 0x10 }, >> +       { 0x9009d, 0x109 }, >> +       { 0x9009e, 0x5 }, >> +       { 0x9009f, 0x7c0 }, >> +       { 0x900a0, 0x109 }, >> +       { 0x900a1, 0x0 }, >> +       { 0x900a2, 0x8140 }, >> +       { 0x900a3, 0x10c }, >> +       { 0x900a4, 0x10 }, >> +       { 0x900a5, 0x8138 }, >> +       { 0x900a6, 0x10c }, >> +       { 0x900a7, 0x8 }, >> +       { 0x900a8, 0x7c8 }, >> +       { 0x900a9, 0x101 }, >> +       { 0x900aa, 0x8 }, >> +       { 0x900ab, 0x448 }, >> +       { 0x900ac, 0x109 }, >> +       { 0x900ad, 0xf }, >> +       { 0x900ae, 0x7c0 }, >> +       { 0x900af, 0x109 }, >> +       { 0x900b0, 0x47 }, >> +       { 0x900b1, 0x630 }, >> +       { 0x900b2, 0x109 }, >> +       { 0x900b3, 0x8 }, >> +       { 0x900b4, 0x618 }, >> +       { 0x900b5, 0x109 }, >> +       { 0x900b6, 0x8 }, >> +       { 0x900b7, 0xe0 }, >> +       { 0x900b8, 0x109 }, >> +       { 0x900b9, 0x0 }, >> +       { 0x900ba, 0x7c8 }, >> +       { 0x900bb, 0x109 }, >> +       { 0x900bc, 0x8 }, >> +       { 0x900bd, 0x8140 }, >> +       { 0x900be, 0x10c }, >> +       { 0x900bf, 0x0 }, >> +       { 0x900c0, 0x1 }, >> +       { 0x900c1, 0x8 }, >> +       { 0x900c2, 0x8 }, >> +       { 0x900c3, 0x4 }, >> +       { 0x900c4, 0x8 }, >> +       { 0x900c5, 0x8 }, >> +       { 0x900c6, 0x7c8 }, >> +       { 0x900c7, 0x101 }, >> +       { 0x90006, 0x0 }, >> +       { 0x90007, 0x0 }, >> +       { 0x90008, 0x8 }, >> +       { 0x90009, 0x0 }, >> +       { 0x9000a, 0x0 }, >> +       { 0x9000b, 0x0 }, >> +       { 0xd00e7, 0x400 }, >> +       { 0x90017, 0x0 }, >> +       { 0x90026, 0x2b }, >> +       { 0x2000b, 0x4b }, >> +       { 0x2000c, 0x96 }, >> +       { 0x2000d, 0x5dc }, >> +       { 0x2000e, 0x2c }, >> +       { 0x12000b, 0x21 }, >> +       { 0x12000c, 0x42 }, >> +       { 0x12000d, 0x29a }, >> +       { 0x12000e, 0x21 }, >> +       { 0x9000c, 0x0 }, >> +       { 0x9000d, 0x173 }, >> +       { 0x9000e, 0x60 }, >> +       { 0x9000f, 0x6110 }, >> +       { 0x90010, 0x2152 }, >> +       { 0x90011, 0xdfbd }, >> +       { 0x90012, 0xffff }, >> +       { 0x90013, 0x6152 }, >> +       { 0x20089, 0x1 }, >> +       { 0x20088, 0x19 }, >> +       { 0xc0080, 0x0 }, >> +       { 0xd0000, 0x1 }, >> +}; >> + >> +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { >> +       { >> +               /* P0 2400mts 1D */ >> +               .drate = 2400, >> +               .fw_type = FW_1D_IMAGE, >> +               .fsp_cfg = ddr_fsp0_cfg, >> +               .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), >> +       }, >> +       { >> +               /* P1 1066mts 1D */ >> +               .drate = 1066, >> +               .fw_type = FW_1D_IMAGE, >> +               .fsp_cfg = ddr_fsp1_cfg, >> +               .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), >> +       }, >> +       { >> +               /* P0 2400mts 2D */ >> +               .drate = 2400, >> +               .fw_type = FW_2D_IMAGE, >> +               .fsp_cfg = ddr_fsp0_2d_cfg, >> +               .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), >> +       }, >> +}; >> + >> +/* ddr timing config params */ >> +struct dram_timing_info dram_timing = { >> +       .ddrc_cfg = ddr_ddrc_cfg, >> +       .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), >> +       .ddrphy_cfg = ddr_ddrphy_cfg, >> +       .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), >> +       .fsp_msg = ddr_dram_fsp_msg, >> +       .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), >> +       .ddrphy_pie = ddr_phy_pie, >> +       .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), >> +       .fsp_table = { 2400, 1066, }, >> +}; >> diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c b/board/variscite/imx8mn_var_som/imx8mn_var_som.c >> new file mode 100644 >> index 00000000000..1d2f8a40590 >> --- /dev/null >> +++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c >> @@ -0,0 +1,35 @@ >> +/* >> + * Copyright 2021 Collabora Ltd. >> + * >> + * SPDX-License-Identifier:    GPL-2.0+ >> + */ >> + >> +#include <common.h> >> +#include <env.h> >> +#include <asm/io.h> >> + >> +#if IS_ENABLED(CONFIG_FEC_MXC) >> +static int setup_fec(void) >> +{ >> +       struct iomuxc_gpr_base_regs *gpr = >> +               (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; >> + >> +       /* Use 125M anatop REF_CLK1 for ENET1, not from external */ >> +       clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); >> + >> +       return 0; >> +} >> +#endif >> + >> +int board_init(void) >> +{ >> +       if (IS_ENABLED(CONFIG_FEC_MXC)) >> +               setup_fec(); >> + >> +       return 0; >> +} >> + >> +int board_mmc_get_env_dev(int devno) >> +{ >> +       return devno; >> +} >> diff --git a/board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg b/board/variscite/imx8mn_var_som/imximage- >> 8mn-ddr4.cfg >> new file mode 100644 >> index 00000000000..a24856eb631 >> --- /dev/null >> +++ b/board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg > > I believe usually that file was just called imximage.cfg. I am not against a target specific name but then your > name does not really seem that target specific. I'm basing my patch on other imx8mn board, which is using the same name pattern here board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg I'd keep it as it is for now. > >> @@ -0,0 +1,12 @@ >> +/* SPDX-License-Identifier: GPL-2.0+ */ >> +/* >> + * Copyright 2021 Collabora Ltd. >> + */ >> + >> +#define __ASSEMBLY__ >> + >> +FIT >> +ROM_VERSION v2 >> +BOOT_FROM sd >> +LOADER u-boot-spl-ddr.bin 0x912000 >> +SECOND_LOADER u-boot.itb 0x40200000 0x60000 > > Not sure what exactly that SECOND_LOADER achieves. Isn't that nowadays handled by binman? You're right, will fix in v2. > >> diff --git a/board/variscite/imx8mn_var_som/spl.c b/board/variscite/imx8mn_var_som/spl.c >> new file mode 100644 >> index 00000000000..f7e17f65127 >> --- /dev/null >> +++ b/board/variscite/imx8mn_var_som/spl.c >> @@ -0,0 +1,104 @@ >> +/* >> + * Copyright 2021 Collabora Ltd. >> + * >> + * SPDX-License-Identifier:    GPL-2.0+ >> + */ >> + >> +#include <hang.h> >> +#include <init.h> >> +#include <spl.h> >> +#include <asm/arch/clock.h> >> +#include <asm/arch/ddr.h> >> +#include <asm/arch/imx8mn_pins.h> >> +#include <asm/arch/sys_proto.h> >> +#include <asm/mach-imx/boot_mode.h> >> +#include <asm/mach-imx/gpio.h> >> + > > That newline does not really serve any purpose. Removed in v2. > >> +#include <dm/device.h> >> +#include <dm/uclass.h> >> + >> +int spl_board_boot_device(enum boot_device boot_dev_spl) >> +{ >> +       return BOOT_DEVICE_BOOTROM; >> +} >> + >> +void spl_dram_init(void) >> +{ >> +       ddr_init(&dram_timing); >> +} >> + >> +void spl_board_init(void) >> +{ >> +       struct udevice *dev; >> +       int ret; >> + >> +       debug("Normal Boot\n"); >> + >> +       ret = uclass_get_device_by_name(UCLASS_CLK, >> +                                       "clock-controller@30380000", >> +                                       &dev); >> +       if (ret < 0) >> +               puts("Failed to find clock node. Check device tree\n"); >> +} >> + >> +#ifdef CONFIG_SPL_LOAD_FIT >> +int board_fit_config_name_match(const char *name) >> +{ >> +       /* Just empty function now - can't decide what to choose */ >> +       debug("%s: %s\n", __func__, name); >> + >> +       return 0; >> +} >> +#endif >> + >> +#define UART_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_FSEL1) >> +#define WDOG_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) >> + >> +static iomux_v3_cfg_t const uart_pads[] = { > > Didn't checkpatch suggest to put that const after static? > > 0 errors, 11 warnings, 2 checks for 0001-imx8mn_var_som-Add-support-for-Variscite-VAR-SOM-MX8.patch: > <patch>:56: warning: added, moved or deleted file(s), does MAINTAINERS need updating? > arch/arm/dts/imx8mn-var-som.dts:283: check: Please don't use multiple blank lines > board/variscite/imx8mn_var_som/ddr4_timing.c:1: warning: Missing or malformed SPDX-License-Identifier tag in > line 1 > board/variscite/imx8mn_var_som/ddr4_timing.c:4: warning: Misplaced SPDX-License-Identifier tag - use line 1 > instead > board/variscite/imx8mn_var_som/imx8mn_var_som.c:1: warning: Missing or malformed SPDX-License-Identifier tag in > line 1 > board/variscite/imx8mn_var_som/imx8mn_var_som.c:4: warning: Misplaced SPDX-License-Identifier tag - use line 1 > instead > board/variscite/imx8mn_var_som/imx8mn_var_som.c:11: warning: Use 'if (IS_ENABLED(CONFIG...))' instead of '#if > or #ifdef' where possible > board/variscite/imx8mn_var_som/spl.c:1: warning: Missing or malformed SPDX-License-Identifier tag in line 1 > board/variscite/imx8mn_var_som/spl.c:4: warning: Misplaced SPDX-License-Identifier tag - use line 1 instead > board/variscite/imx8mn_var_som/spl.c:44: warning: Use 'if (IS_ENABLED(CONFIG...))' instead of '#if or #ifdef' > where possible > board/variscite/imx8mn_var_som/spl.c:57: warning: Move const after static - use 'static const iomux_v3_cfg_t' > board/variscite/imx8mn_var_som/spl.c:62: warning: Move const after static - use 'static const iomux_v3_cfg_t' > include/configs/imx8mn_var_som.h:37: check: Macro argument reuse 'func' - possible side-effects? > checkpatch.pl found 0 error(s), 11 warning(s), 2 checks(s) > > You might want to address all of those suggestions (;-p). Ugh, sorry. All fixed in v2. > >> +       IMX8MN_PAD_UART4_RXD__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), >> +       IMX8MN_PAD_UART4_TXD__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), >> +}; >> + >> +static iomux_v3_cfg_t const wdog_pads[] = { > > Ditto. Done. > >> +       IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), >> +}; >> + >> +int board_early_init_f(void) >> +{ >> +       struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; >> + >> +       imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); >> +       set_wdog_reset(wdog); >> + >> +       imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); >> +       init_uart_clk(3); >> + >> +       return 0; >> +} >> + >> +void board_init_f(ulong dummy) >> +{ >> +       int ret; >> + >> +       /* Clear the BSS. */ >> +       memset(__bss_start, 0, __bss_end - __bss_start); >> + >> +       arch_cpu_init(); >> + >> +       board_early_init_f(); >> + >> +       timer_init(); >> + >> +       preloader_console_init(); >> + >> +       ret = spl_init(); >> +       if (ret) { >> +               debug("spl_init() failed: %d\n", ret); >> +               hang(); >> +       } >> + >> +       /* DDR initialization */ >> +       spl_dram_init(); >> + >> +       board_init_r(NULL, 0); >> +} >> diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig >> new file mode 100644 >> index 00000000000..41d317fd5b0 >> --- /dev/null >> +++ b/configs/imx8mn_var_som_defconfig >> @@ -0,0 +1,98 @@ >> +CONFIG_ARM=y >> +CONFIG_ARCH_IMX8M=y >> +CONFIG_SYS_TEXT_BASE=0x40200000 >> +CONFIG_SYS_MALLOC_LEN=0x2000000 >> +CONFIG_SYS_MALLOC_F_LEN=0x10000 >> +CONFIG_SPL_GPIO=y >> +CONFIG_SPL_LIBCOMMON_SUPPORT=y >> +CONFIG_SPL_LIBGENERIC_SUPPORT=y >> +CONFIG_NR_DRAM_BANKS=1 >> +CONFIG_ENV_SIZE=0x2000 >> +CONFIG_ENV_OFFSET=0xFFFFDE00 >> +CONFIG_DM_GPIO=y >> +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-var-som" >> +CONFIG_SPL_TEXT_BASE=0x912000 >> +CONFIG_TARGET_IMX8MN_VAR_SOM=y >> +CONFIG_SPL_MMC=y >> +CONFIG_SPL_SERIAL=y >> +CONFIG_SPL_DRIVERS_MISC=y >> +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 >> +CONFIG_SPL=y >> +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 >> +CONFIG_DISTRO_DEFAULTS=y >> +CONFIG_SYS_LOAD_ADDR=0x40480000 >> +CONFIG_FIT=y >> +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 >> +CONFIG_SPL_LOAD_FIT=y >> +# CONFIG_USE_SPL_FIT_GENERATOR is not set >> +CONFIG_OF_SYSTEM_SETUP=y >> +CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-var-som-symphony.dtb" >> +CONFIG_ARCH_MISC_INIT=y >> +CONFIG_SPL_BOARD_INIT=y >> +CONFIG_SPL_BOOTROM_SUPPORT=y >> +CONFIG_SPL_SEPARATE_BSS=y >> +CONFIG_SPL_I2C=y >> +CONFIG_SPL_POWER=y >> +CONFIG_SPL_WATCHDOG=y >> +CONFIG_SYS_PROMPT="> " >> +CONFIG_CMD_FUSE=y >> +CONFIG_CMD_MMC=y >> +CONFIG_CMD_USB=y >> +CONFIG_CMD_USB_MASS_STORAGE=y >> +CONFIG_OF_CONTROL=y >> +CONFIG_SPL_OF_CONTROL=y >> +CONFIG_ENV_IS_IN_MMC=y >> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y >> +CONFIG_SYS_MMC_ENV_DEV=2 >> +CONFIG_SYS_MMC_ENV_PART=1 >> +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y >> +CONFIG_NET_RANDOM_ETHADDR=y >> +CONFIG_SPL_DM=y >> +CONFIG_REGMAP=y >> +CONFIG_SYSCON=y >> +CONFIG_SPL_CLK_COMPOSITE_CCF=y >> +CONFIG_CLK_COMPOSITE_CCF=y >> +CONFIG_SPL_CLK_IMX8MN=y >> +CONFIG_CLK_IMX8MN=y >> +CONFIG_USB_FUNCTION_FASTBOOT=y >> +CONFIG_FASTBOOT_BUF_ADDR=0x40480000 >> +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 >> +CONFIG_FASTBOOT_FLASH=y >> +CONFIG_FASTBOOT_UUU_SUPPORT=y >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=2 >> +CONFIG_MXC_GPIO=y >> +CONFIG_DM_I2C=y >> +CONFIG_SUPPORT_EMMC_BOOT=y >> +CONFIG_MMC_IO_VOLTAGE=y >> +CONFIG_MMC_UHS_SUPPORT=y >> +CONFIG_MMC_HS400_ES_SUPPORT=y >> +CONFIG_MMC_HS400_SUPPORT=y >> +CONFIG_FSL_ESDHC_IMX=y >> +CONFIG_PHYLIB=y >> +CONFIG_PHY_ATHEROS=y >> +CONFIG_DM_ETH=y >> +CONFIG_PHY_GIGE=y >> +CONFIG_FEC_MXC=y >> +CONFIG_MII=y >> +CONFIG_PINCTRL=y >> +CONFIG_SPL_PINCTRL=y >> +CONFIG_PINCTRL_IMX8M=y >> +CONFIG_DM_PMIC=y >> +CONFIG_DM_PMIC_BD71837=y >> +CONFIG_SPL_DM_PMIC_BD71837=y >> +CONFIG_DM_REGULATOR=y >> +CONFIG_DM_REGULATOR_FIXED=y >> +CONFIG_DM_REGULATOR_GPIO=y >> +CONFIG_MXC_UART=y >> +CONFIG_SYSRESET=y >> +CONFIG_SYSRESET_PSCI=y >> +CONFIG_SYSRESET_WATCHDOG=y >> +CONFIG_USB=y >> +CONFIG_USB_EHCI_HCD=y >> +CONFIG_USB_GADGET=y >> +CONFIG_USB_GADGET_MANUFACTURER="FSL" >> +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 >> +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 >> +CONFIG_CI_UDC=y >> +CONFIG_IMX_WATCHDOG=y >> +CONFIG_OF_LIBFDT_OVERLAY=y >> diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h >> new file mode 100644 >> index 00000000000..0ba1af135ff >> --- /dev/null >> +++ b/include/configs/imx8mn_var_som.h >> @@ -0,0 +1,106 @@ >> +/* SPDX-License-Identifier: GPL-2.0+ */ >> +/* >> + * Copyright 2021 Collabora Ltd. >> + */ >> + >> +#ifndef __IMX8MN_VAR_SOM_H >> +#define __IMX8MN_VAR_SOM_H >> + >> +#include <linux/sizes.h> >> +#include <linux/stringify.h> >> +#include <asm/arch/imx-regs.h> >> + >> +#define CONFIG_SYS_BOOTM_LEN           (32 * SZ_1M) >> + >> +#define CONFIG_SPL_MAX_SIZE            (148 * SZ_1K) >> +#define CONFIG_SYS_MONITOR_LEN         SZ_512K >> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR >> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR                0x300 >> +#define CONFIG_SYS_UBOOT_BASE  \ >> +       (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) >> + >> +#ifdef CONFIG_SPL_BUILD >> + >> +#define CONFIG_SPL_STACK               0x980000 >> +#define CONFIG_SPL_BSS_START_ADDR      0x950000 >> +#define CONFIG_SPL_BSS_MAX_SIZE                SZ_8K   /* 8 KB */ > > Once using those SZ macros those comments don't really make much sense any longer. Agreed :-) > >> +#define CONFIG_SYS_SPL_MALLOC_START    0x42200000 >> +#define CONFIG_SYS_SPL_MALLOC_SIZE     SZ_512K /* 512 KB */ > > Ditto. Done. > >> + >> +/* For RAW image gives a error info not panic */ >> +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE >> + >> +#endif /* CONFIG_SPL_BUILD */ >> + >> +#ifndef CONFIG_SPL_BUILD >> + >> +#define BOOT_TARGET_DEVICES(func) \ >> +       func(MMC, mmc, 1) \ >> +       func(MMC, mmc, 2) \ >> +       func(MMC, mmc, 0) \ >> +       func(PXE, pxe, na) \ >> +       func(DHCP, dhcp, na) \ >> + >> +#include <config_distro_bootcmd.h> >> + >> +#endif /* !CONFIG_SPL_BUILD */ >> + >> +/* ENET */ >> +#if defined(CONFIG_FEC_MXC) >> +#define CONFIG_ETHPRIME                        "FEC" >> +#define CONFIG_FEC_XCV_TYPE            RGMII >> +#endif /* CONFIG_FEC_MXC */ >> + >> +#define MEM_LAYOUT_ENV_SETTINGS \ >> +       "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ >> +       "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ >> +       "ramdisk_addr_r=0x43800000\0" \ >> +       "fdt_addr_r=0x43000000\0" \ >> +       "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ >> +       "fastboot_partition_alias_all=" \ >> +               __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) ".0:0\0" \ >> +       "fastboot_partition_alias_bootloader=" \ >> +               __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) ".1:0\0" \ >> +       "emmc_dev=" __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) "\0" \ >> +       "emmc_ack=1\0" \ >> +       "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ >> + >> +/* Initial environment variables */ >> +#define CONFIG_EXTRA_ENV_SETTINGS \ >> +       MEM_LAYOUT_ENV_SETTINGS \ >> +       BOOTENV >> + >> +/* Link Definitions */ >> + >> +#define CONFIG_SYS_INIT_RAM_ADDR       0x40000000 >> +#define CONFIG_SYS_INIT_RAM_SIZE       0x80000 > > SZ_512K > Done. >> +#define CONFIG_SYS_INIT_SP_OFFSET \ >> +       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) >> +#define CONFIG_SYS_INIT_SP_ADDR \ >> +       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) >> + >> +#define CONFIG_SYS_SDRAM_BASE          0x40000000 >> +#define PHYS_SDRAM                     0x40000000 >> +#define PHYS_SDRAM_SIZE                        SZ_1G /* 1GB DDR */ >> + >> +#define CONFIG_BAUDRATE                        115200 >> + >> +#define CONFIG_MXC_UART_BASE           UART4_BASE_ADDR >> + >> +/* Monitor Command Prompt */ >> +#define CONFIG_SYS_CBSIZE              2048 > > SZ_2K Done. > >> +#define CONFIG_SYS_MAXARGS             64 >> +#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE >> +#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \ >> +                                       sizeof(CONFIG_SYS_PROMPT) + 16) >> + >> +/* USDHC */ >> +#define CONFIG_FSL_USDHC >> + >> +#define CONFIG_SYS_FSL_USDHC_NUM       2 >> +#define CONFIG_SYS_FSL_ESDHC_ADDR      0 >> + >> +/* I2C */ >> +#define CONFIG_SYS_I2C_SPEED           400000 >> + >> +#endif /* __IMX8MN_VAR_SOM_H */ > > [1] https://marc.info/?l=u-boot&m=163494450717531 > > Cheers > > Marcel > Thanks a lot for the quick feedback :-) Will submit v2 right away. Regards, Ariel
On Tue, Nov 2, 2021 at 8:19 PM Ariel D'Alessandro <ariel.dalessandro@collabora.com> wrote: > --- /dev/null > +++ b/arch/arm/dts/imx8mn-var-som.dts In the Linux kernel, this is called imx8mn-var-som.dtsi. > @@ -0,0 +1,425 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2021 Collabora Ltd. In the Linux kernel it has: // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright 2019 NXP * Copyright 2019-2020 Variscite Ltd. * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org> */ I suggest you pick the dts directly from the kernel.
On 11/15/21 6:39 PM, Fabio Estevam wrote: > On Tue, Nov 2, 2021 at 8:19 PM Ariel D'Alessandro > <ariel.dalessandro@collabora.com> wrote: > >> --- /dev/null >> +++ b/arch/arm/dts/imx8mn-var-som.dts > > In the Linux kernel, this is called imx8mn-var-som.dtsi. > >> @@ -0,0 +1,425 @@ >> +// SPDX-License-Identifier: GPL-2.0+ >> +/* >> + * Copyright 2021 Collabora Ltd. > > In the Linux kernel it has: > > // SPDX-License-Identifier: (GPL-2.0+ OR MIT) > /* > * Copyright 2019 NXP > * Copyright 2019-2020 Variscite Ltd. > * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org> > */ > > I suggest you pick the dts directly from the kernel. Makes sense. Will address in v3.
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cc34da7bd83..dfa034be80f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -901,6 +901,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mn-ddr4-evk.dtb \ imx8mq-cm.dtb \ imx8mn-evk.dtb \ + imx8mn-var-som.dtb \ imx8mq-evk.dtb \ imx8mm-beacon-kit.dtb \ imx8mn-beacon-kit.dtb \ diff --git a/arch/arm/dts/imx8mn-var-som-u-boot.dtsi b/arch/arm/dts/imx8mn-var-som-u-boot.dtsi new file mode 100644 index 00000000000..73df408bc82 --- /dev/null +++ b/arch/arm/dts/imx8mn-var-som-u-boot.dtsi @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 Collabora Ltd. + */ + +/ { + binman: binman { + multiple-images; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; +}; + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { + u-boot,dm-spl; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&aips4 { + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; + u-boot,dm-pre-reloc; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&osc_24m { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; + +&pinctrl_reg_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_uart4 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&pinctrl_wdog { + u-boot,dm-spl; +}; + +&uart4 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; +}; + +&usdhc3 { + u-boot,dm-spl; +}; + +&wdog1 { + u-boot,dm-spl; +}; + +&binman { + u-boot-spl-ddr { + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + align-size = <4>; + align = <4>; + + u-boot-spl { + align-end = <4>; + }; + + blob_1: blob-ext@1 { + filename = "ddr4_imem_1d.bin"; + size = <0x8000>; + }; + + blob_2: blob-ext@2 { + filename = "ddr4_dmem_1d.bin"; + size = <0x4000>; + }; + + blob_3: blob-ext@3 { + filename = "ddr4_imem_2d.bin"; + size = <0x8000>; + }; + + blob_4: blob-ext@4 { + filename = "ddr4_dmem_2d.bin"; + size = <0x4000>; + }; + }; + + itb { + filename = "u-boot.itb"; + + fit { + description = "Configuration to load ATF before U-Boot"; + #address-cells = <1>; + fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; + + images { + uboot { + description = "U-Boot (64-bit)"; + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = <CONFIG_SYS_TEXT_BASE>; + + uboot_blob: blob-ext { + filename = "u-boot-nodtb.bin"; + }; + }; + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <0x960000>; + entry = <0x960000>; + + atf_blob: blob-ext { + filename = "bl31.bin"; + }; + }; + + fdt { + description = "NAME"; + type = "flat_dt"; + compression = "none"; + + uboot_fdt_blob: blob-ext { + filename = "u-boot.dtb"; + }; + }; + }; + + configurations { + default = "conf"; + + conf { + description = "NAME"; + firmware = "uboot"; + loadables = "atf"; + fdt = "fdt"; + }; + }; + }; + }; + + flash { + mkimage { + args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000"; + + blob { + filename = "u-boot-spl-ddr.bin"; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx8mn-var-som.dts b/arch/arm/dts/imx8mn-var-som.dts new file mode 100644 index 00000000000..e094d25af8c --- /dev/null +++ b/arch/arm/dts/imx8mn-var-som.dts @@ -0,0 +1,425 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 Collabora Ltd. + */ + +/dts-v1/; + +#include "imx8mn.dtsi" + +/ { + model = "Variscite VAR-SOM-MX8MN module"; + compatible = "variscite,var-som-mx8mn", "fsl,imx8mn"; + + chosen { + bootargs = "console=ttymxc3,115200 earlycon=ec_imx6q,0x30a60000,115200"; + stdout-path = &uart4; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_eth_phy: regulator-eth-phy { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_eth_phy>; + regulator-name = "eth_phy_pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii"; + phy-handle = <ðphy>; + phy-supply = <®_eth_phy>; + phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio2>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3_reg: BUCK3 { + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "buck4"; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "buck5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "buck6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +/* Console */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +/* SD */ +&usdhc2 { + assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141 + >; + }; + + pinctrl_reg_eth_phy: regethphygrp { + fsl,pins = < + MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 + >; + }; + + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 + >; + }; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 276b8bd9742..82a5ab8ad00 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -108,6 +108,14 @@ config TARGET_PICO_IMX8MQ select IMX8MQ select IMX8M_LPDDR4 +config TARGET_IMX8MN_VAR_SOM + bool "imx8mn_var_som" + select BINMAN + select IMX8MN + select SUPPORT_SPL + select IMX8M_DDR4 + select IMX8M_BOARD_INIT_DRAM + config TARGET_VERDIN_IMX8MM bool "Support Toradex Verdin iMX8M Mini module" select BINMAN @@ -171,6 +179,7 @@ source "board/phytec/phycore_imx8mm/Kconfig" source "board/phytec/phycore_imx8mp/Kconfig" source "board/ronetix/imx8mq-cm/Kconfig" source "board/technexion/pico-imx8mq/Kconfig" +source "board/variscite/imx8mn_var_som/Kconfig" source "board/toradex/verdin-imx8mm/Kconfig" endif diff --git a/board/variscite/imx8mn_var_som/Kconfig b/board/variscite/imx8mn_var_som/Kconfig new file mode 100644 index 00000000000..cfe6fc8c2c7 --- /dev/null +++ b/board/variscite/imx8mn_var_som/Kconfig @@ -0,0 +1,17 @@ +if TARGET_IMX8MN_VAR_SOM + +config SYS_BOARD + default "imx8mn_var_som" + +config SYS_VENDOR + default "variscite" + +config SYS_CONFIG_NAME + default "imx8mn_var_som" + +config IMX_CONFIG + default "board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/variscite/imx8mn_var_som/Makefile b/board/variscite/imx8mn_var_som/Makefile new file mode 100644 index 00000000000..a8b6a343ffc --- /dev/null +++ b/board/variscite/imx8mn_var_som/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2021 Collabora Ltd. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mn_var_som.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += ddr4_timing.o +endif diff --git a/board/variscite/imx8mn_var_som/ddr4_timing.c b/board/variscite/imx8mn_var_som/ddr4_timing.c new file mode 100644 index 00000000000..6d3d1805c89 --- /dev/null +++ b/board/variscite/imx8mn_var_som/ddr4_timing.c @@ -0,0 +1,529 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400000, 0x81040010 }, + { 0x3d400030, 0x20 }, + { 0x3d400034, 0x221306 }, + { 0x3d400050, 0x210070 }, + { 0x3d400054, 0x10008 }, + { 0x3d400060, 0x0 }, + { 0x3d400064, 0x9200d2 }, + { 0x3d4000c0, 0x0 }, + { 0x3d4000c4, 0x1000 }, + { 0x3d4000d0, 0xc0030126 }, + { 0x3d4000d4, 0x770000 }, + { 0x3d4000dc, 0x8340105 }, + { 0x3d4000e0, 0x180200 }, + { 0x3d4000e4, 0x110000 }, + { 0x3d4000e8, 0x2000600 }, + { 0x3d4000ec, 0x810 }, + { 0x3d4000f0, 0x20 }, + { 0x3d4000f4, 0xec7 }, + { 0x3d400100, 0x11122914 }, + { 0x3d400104, 0x4051c }, + { 0x3d400108, 0x608050d }, + { 0x3d40010c, 0x400c }, + { 0x3d400110, 0x8030409 }, + { 0x3d400114, 0x6060403 }, + { 0x3d40011c, 0x606 }, + { 0x3d400120, 0x5050d08 }, + { 0x3d400124, 0x2040a }, + { 0x3d40012c, 0x1409010e }, + { 0x3d400130, 0x8 }, + { 0x3d40013c, 0x0 }, + { 0x3d400180, 0x1000040 }, + { 0x3d400184, 0x493e }, + { 0x3d400190, 0x38b8207 }, + { 0x3d400194, 0x2020303 }, + { 0x3d400198, 0x7f04011 }, + { 0x3d40019c, 0xb0 }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0x48005a }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x1 }, + { 0x3d4001b4, 0xb07 }, + { 0x3d4001b8, 0x4 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x0 }, + { 0x3d400200, 0x3f1f }, + { 0x3d400204, 0x3f0909 }, + { 0x3d400208, 0x700 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400220, 0x3f01 }, + { 0x3d400240, 0x6000610 }, + { 0x3d400244, 0x1323 }, + { 0x3d400400, 0x100 }, + { 0x3d400250, 0x317d1a07 }, + { 0x3d400254, 0xf }, + { 0x3d40025c, 0x2a001b76 }, + { 0x3d400264, 0x7300b473 }, + { 0x3d40026c, 0x30000e06 }, + { 0x3d400300, 0x14 }, + { 0x3d40036c, 0x10 }, + { 0x3d400404, 0x13193 }, + { 0x3d400408, 0x6096 }, + { 0x3d400490, 0x1 }, + { 0x3d400494, 0x2000c00 }, + { 0x3d400498, 0x3c00db }, + { 0x3d40049c, 0x100009 }, + { 0x3d4004a0, 0x2 }, + { 0x3d402050, 0x210070 }, + { 0x3d402064, 0x40005e }, + { 0x3d4020dc, 0x40105 }, + { 0x3d4020e0, 0x0 }, + { 0x3d4020e8, 0x2000600 }, + { 0x3d4020ec, 0x10 }, + { 0x3d402100, 0xb081209 }, + { 0x3d402104, 0x2020d }, + { 0x3d402108, 0x5050309 }, + { 0x3d40210c, 0x400c }, + { 0x3d402110, 0x5030206 }, + { 0x3d402114, 0x3030202 }, + { 0x3d40211c, 0x303 }, + { 0x3d402120, 0x3030d04 }, + { 0x3d402124, 0x20208 }, + { 0x3d40212c, 0x1005010e }, + { 0x3d402130, 0x8 }, + { 0x3d40213c, 0x0 }, + { 0x3d402180, 0x1000040 }, + { 0x3d402190, 0x3858204 }, + { 0x3d402194, 0x2020303 }, + { 0x3d4021b4, 0x504 }, + { 0x3d4021b8, 0x4 }, + { 0x3d402240, 0x6000604 }, + { 0x3d4020f4, 0xec7 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x1005f, 0x2fd }, + { 0x1015f, 0x2fd }, + { 0x1105f, 0x2fd }, + { 0x1115f, 0x2fd }, + { 0x11005f, 0x2fd }, + { 0x11015f, 0x2fd }, + { 0x11105f, 0x2fd }, + { 0x11115f, 0x2fd }, + { 0x55, 0x355 }, + { 0x1055, 0x355 }, + { 0x2055, 0x355 }, + { 0x3055, 0x355 }, + { 0x4055, 0x55 }, + { 0x5055, 0x55 }, + { 0x6055, 0x355 }, + { 0x7055, 0x355 }, + { 0x8055, 0x355 }, + { 0x9055, 0x355 }, + { 0x200c5, 0xa }, + { 0x1200c5, 0x6 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x1 }, + { 0x20024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x6 }, + { 0x120056, 0xa }, + { 0x1004d, 0x1a }, + { 0x1014d, 0x1a }, + { 0x1104d, 0x1a }, + { 0x1114d, 0x1a }, + { 0x11004d, 0x1a }, + { 0x11014d, 0x1a }, + { 0x11104d, 0x1a }, + { 0x11114d, 0x1a }, + { 0x10049, 0xe38 }, + { 0x10149, 0xe38 }, + { 0x11049, 0xe38 }, + { 0x11149, 0xe38 }, + { 0x110049, 0xe38 }, + { 0x110149, 0xe38 }, + { 0x111049, 0xe38 }, + { 0x111149, 0xe38 }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x1 }, + { 0x20075, 0x2 }, + { 0x20050, 0x0 }, + { 0x20008, 0x258 }, + { 0x120008, 0x10a }, + { 0x20088, 0x9 }, + { 0x200b2, 0x268 }, + { 0x10043, 0x5b1 }, + { 0x10143, 0x5b1 }, + { 0x11043, 0x5b1 }, + { 0x11143, 0x5b1 }, + { 0x1200b2, 0x268 }, + { 0x110043, 0x5b1 }, + { 0x110143, 0x5b1 }, + { 0x111043, 0x5b1 }, + { 0x111143, 0x5b1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x20019, 0x5 }, + { 0x120019, 0x5 }, + { 0x200f0, 0x5555 }, + { 0x200f1, 0x5555 }, + { 0x200f2, 0x5555 }, + { 0x200f3, 0x5555 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x5555 }, + { 0x200f6, 0x5555 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x2005b, 0x7529 }, + { 0x2005c, 0x0 }, + { 0x200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x200cc, 0x1f7 }, + { 0x1200c7, 0x21 }, + { 0x1200ca, 0x24 }, + { 0x1200cc, 0x1f7 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x31f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x834 }, + { 0x54030, 0x105 }, + { 0x54031, 0x18 }, + { 0x54032, 0x200 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x810 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x42a }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x4 }, + { 0x54030, 0x105 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x10 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x61 }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x5400e, 0x1f7f }, + { 0x54012, 0x1 }, + { 0x5402f, 0x834 }, + { 0x54030, 0x105 }, + { 0x54031, 0x18 }, + { 0x54032, 0x200 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x810 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x2 }, + { 0x90033, 0x10 }, + { 0x90034, 0x139 }, + { 0x90035, 0xb }, + { 0x90036, 0x7c0 }, + { 0x90037, 0x139 }, + { 0x90038, 0x44 }, + { 0x90039, 0x633 }, + { 0x9003a, 0x159 }, + { 0x9003b, 0x14f }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x47 }, + { 0x9003f, 0x633 }, + { 0x90040, 0x149 }, + { 0x90041, 0x4f }, + { 0x90042, 0x633 }, + { 0x90043, 0x179 }, + { 0x90044, 0x8 }, + { 0x90045, 0xe0 }, + { 0x90046, 0x109 }, + { 0x90047, 0x0 }, + { 0x90048, 0x7c8 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x1 }, + { 0x9004c, 0x8 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x45a }, + { 0x9004f, 0x9 }, + { 0x90050, 0x0 }, + { 0x90051, 0x448 }, + { 0x90052, 0x109 }, + { 0x90053, 0x40 }, + { 0x90054, 0x633 }, + { 0x90055, 0x179 }, + { 0x90056, 0x1 }, + { 0x90057, 0x618 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40c0 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x149 }, + { 0x9005c, 0x8 }, + { 0x9005d, 0x4 }, + { 0x9005e, 0x48 }, + { 0x9005f, 0x4040 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x0 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x40 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x10 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x18 }, + { 0x9006b, 0x0 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x78 }, + { 0x9006e, 0x549 }, + { 0x9006f, 0x633 }, + { 0x90070, 0x159 }, + { 0x90071, 0xd49 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0x94a }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x441 }, + { 0x90078, 0x633 }, + { 0x90079, 0x149 }, + { 0x9007a, 0x42 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x1 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x0 }, + { 0x90081, 0xe0 }, + { 0x90082, 0x109 }, + { 0x90083, 0xa }, + { 0x90084, 0x10 }, + { 0x90085, 0x109 }, + { 0x90086, 0x9 }, + { 0x90087, 0x3c0 }, + { 0x90088, 0x149 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x159 }, + { 0x9008c, 0x18 }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x0 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x109 }, + { 0x90092, 0x18 }, + { 0x90093, 0x4 }, + { 0x90094, 0x48 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x58 }, + { 0x90098, 0xb }, + { 0x90099, 0x10 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x1 }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x5 }, + { 0x9009f, 0x7c0 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x0 }, + { 0x900a2, 0x8140 }, + { 0x900a3, 0x10c }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x8138 }, + { 0x900a6, 0x10c }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7c8 }, + { 0x900a9, 0x101 }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x448 }, + { 0x900ac, 0x109 }, + { 0x900ad, 0xf }, + { 0x900ae, 0x7c0 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x47 }, + { 0x900b1, 0x630 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x8 }, + { 0x900b4, 0x618 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0xe0 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x0 }, + { 0x900ba, 0x7c8 }, + { 0x900bb, 0x109 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x8140 }, + { 0x900be, 0x10c }, + { 0x900bf, 0x0 }, + { 0x900c0, 0x1 }, + { 0x900c1, 0x8 }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x8 }, + { 0x900c5, 0x8 }, + { 0x900c6, 0x7c8 }, + { 0x900c7, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x90026, 0x2b }, + { 0x2000b, 0x4b }, + { 0x2000c, 0x96 }, + { 0x2000d, 0x5dc }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x21 }, + { 0x12000c, 0x42 }, + { 0x12000d, 0x29a }, + { 0x12000e, 0x21 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0xffff }, + { 0x90013, 0x6152 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 }, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1066mts 1D */ + .drate = 1066, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 1066, }, +}; diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c b/board/variscite/imx8mn_var_som/imx8mn_var_som.c new file mode 100644 index 00000000000..1d2f8a40590 --- /dev/null +++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c @@ -0,0 +1,35 @@ +/* + * Copyright 2021 Collabora Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <env.h> +#include <asm/io.h> + +#if IS_ENABLED(CONFIG_FEC_MXC) +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); + + return 0; +} +#endif + +int board_init(void) +{ + if (IS_ENABLED(CONFIG_FEC_MXC)) + setup_fec(); + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} diff --git a/board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg b/board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg new file mode 100644 index 00000000000..a24856eb631 --- /dev/null +++ b/board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 Collabora Ltd. + */ + +#define __ASSEMBLY__ + +FIT +ROM_VERSION v2 +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x912000 +SECOND_LOADER u-boot.itb 0x40200000 0x60000 diff --git a/board/variscite/imx8mn_var_som/spl.c b/board/variscite/imx8mn_var_som/spl.c new file mode 100644 index 00000000000..f7e17f65127 --- /dev/null +++ b/board/variscite/imx8mn_var_som/spl.c @@ -0,0 +1,104 @@ +/* + * Copyright 2021 Collabora Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <hang.h> +#include <init.h> +#include <spl.h> +#include <asm/arch/clock.h> +#include <asm/arch/ddr.h> +#include <asm/arch/imx8mn_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/gpio.h> + +#include <dm/device.h> +#include <dm/uclass.h> + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_dram_init(void) +{ + ddr_init(&dram_timing); +} + +void spl_board_init(void) +{ + struct udevice *dev; + int ret; + + debug("Normal Boot\n"); + + ret = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@30380000", + &dev); + if (ret < 0) + puts("Failed to find clock node. Check device tree\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MN_PAD_UART4_RXD__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MN_PAD_UART4_TXD__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + init_uart_clk(3); + + return 0; +} + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig new file mode 100644 index 00000000000..41d317fd5b0 --- /dev/null +++ b/configs/imx8mn_var_som_defconfig @@ -0,0 +1,98 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-var-som" +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_TARGET_IMX8MN_VAR_SOM=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-var-som-symphony.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="> " +CONFIG_CMD_FUSE=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MN=y +CONFIG_CLK_IMX8MN=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x40480000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=2 +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_BD71837=y +CONFIG_SPL_DM_PMIC_BD71837=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h new file mode 100644 index 00000000000..0ba1af135ff --- /dev/null +++ b/include/configs/imx8mn_var_som.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 Collabora Ltd. + */ + +#ifndef __IMX8MN_VAR_SOM_H +#define __IMX8MN_VAR_SOM_H + +#include <linux/sizes.h> +#include <linux/stringify.h> +#include <asm/arch/imx-regs.h> + +#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) + +#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD + +#define CONFIG_SPL_STACK 0x980000 +#define CONFIG_SPL_BSS_START_ADDR 0x950000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ + +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif /* CONFIG_SPL_BUILD */ + +#ifndef CONFIG_SPL_BUILD + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + func(MMC, mmc, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) \ + +#include <config_distro_bootcmd.h> + +#endif /* !CONFIG_SPL_BUILD */ + +/* ENET */ +#if defined(CONFIG_FEC_MXC) +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_XCV_TYPE RGMII +#endif /* CONFIG_FEC_MXC */ + +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramdisk_addr_r=0x43800000\0" \ + "fdt_addr_r=0x43000000\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fastboot_partition_alias_all=" \ + __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) ".0:0\0" \ + "fastboot_partition_alias_bootloader=" \ + __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) ".1:0\0" \ + "emmc_dev=" __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) "\0" \ + "emmc_ack=1\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + MEM_LAYOUT_ENV_SETTINGS \ + BOOTENV + +/* Link Definitions */ + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* USDHC */ +#define CONFIG_FSL_USDHC + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +/* I2C */ +#define CONFIG_SYS_I2C_SPEED 400000 + +#endif /* __IMX8MN_VAR_SOM_H */
Add support for iMX8MN VAR-SOM-MX8M-NANO board. Enables support for: - 1GiB DDR4 RAM - 16 GiB eMMC - SD card - Gigabit ethernet - USBOTG1 peripheral - fastboot Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8mn-var-som-u-boot.dtsi | 220 ++++++++ arch/arm/dts/imx8mn-var-som.dts | 425 ++++++++++++++ arch/arm/mach-imx/imx8m/Kconfig | 9 + board/variscite/imx8mn_var_som/Kconfig | 17 + board/variscite/imx8mn_var_som/Makefile | 12 + board/variscite/imx8mn_var_som/ddr4_timing.c | 529 ++++++++++++++++++ .../variscite/imx8mn_var_som/imx8mn_var_som.c | 35 ++ .../imx8mn_var_som/imximage-8mn-ddr4.cfg | 12 + board/variscite/imx8mn_var_som/spl.c | 104 ++++ configs/imx8mn_var_som_defconfig | 98 ++++ include/configs/imx8mn_var_som.h | 106 ++++ 12 files changed, 1568 insertions(+) create mode 100644 arch/arm/dts/imx8mn-var-som-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-var-som.dts create mode 100644 board/variscite/imx8mn_var_som/Kconfig create mode 100644 board/variscite/imx8mn_var_som/Makefile create mode 100644 board/variscite/imx8mn_var_som/ddr4_timing.c create mode 100644 board/variscite/imx8mn_var_som/imx8mn_var_som.c create mode 100644 board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg create mode 100644 board/variscite/imx8mn_var_som/spl.c create mode 100644 configs/imx8mn_var_som_defconfig create mode 100644 include/configs/imx8mn_var_som.h