| Message ID | 20211101090755.23762-4-alpernebiyasak@gmail.com |
|---|---|
| State | Superseded |
| Delegated to: | Kever Yang |
| Headers | show |
| Series | rockchip: sdhci: Add HS400 Enhanced Strobe support | expand |
On 11/1/21 6:07 PM, Alper Nebi Yasak wrote: > On RK3568, a register bit must be set to enable Enhanced Strobe. > However, it appears that the address of this register may differ from > vendor to vendor and should be read from the underlying MMC IP. > Let the Rockchip SDHCI driver read this address and set the relevant bit > when Enhanced Strobe configuration is requested. > > This is mostly ported from Linux' Synopsys DWC MSHC driver which happens > to be the underlying IP. (drivers/mmc/host/sdhci-of-dwcmshc.c in Linux > tree). > > Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> > --- > Merely build-tested as I don't have a RK3568 board. If someone can test this patch on RK3568 board, it will be more better. Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Best Regards, Jaehoon Chung > > drivers/mmc/rockchip_sdhci.c | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c > index 7457255fa080..c95f95578672 100644 > --- a/drivers/mmc/rockchip_sdhci.c > +++ b/drivers/mmc/rockchip_sdhci.c > @@ -45,6 +45,13 @@ > #define ARASAN_VENDOR_REGISTER 0x78 > #define ARASAN_VENDOR_ENHANCED_STROBE BIT(0) > > +/* DWC IP vendor area 1 pointer */ > +#define DWCMSHC_P_VENDOR_AREA1 0xe8 > +#define DWCMSHC_AREA1_MASK GENMASK(11, 0) > +/* Offset inside the vendor area 1 */ > +#define DWCMSHC_EMMC_CONTROL 0x2c > +#define DWCMSHC_ENHANCED_STROBE BIT(8) > + > /* Rockchip specific Registers */ > #define DWCMSHC_EMMC_DLL_CTRL 0x800 > #define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1) > @@ -284,6 +291,21 @@ static int rk3568_emmc_get_phy(struct udevice *dev) > return 0; > } > > +static int rk3568_set_enhanced_strobe(struct sdhci_host *host) > +{ > + u32 vendor; > + int reg; > + > + reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK) > + + DWCMSHC_EMMC_CONTROL; > + > + vendor = sdhci_readl(host, reg); > + vendor |= DWCMSHC_ENHANCED_STROBE; > + sdhci_writel(host, vendor, reg); > + > + return 0; > +} > + > static int rockchip_sdhci_set_ios_post(struct sdhci_host *host) > { > struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); > @@ -473,6 +495,7 @@ static const struct sdhci_data rk3568_data = { > .emmc_set_clock = rk3568_sdhci_emmc_set_clock, > .get_phy = rk3568_emmc_get_phy, > .emmc_phy_init = rk3568_emmc_phy_init, > + .set_enhanced_strobe = rk3568_set_enhanced_strobe, > }; > > static const struct udevice_id sdhci_ids[] = { >
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index 7457255fa080..c95f95578672 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -45,6 +45,13 @@ #define ARASAN_VENDOR_REGISTER 0x78 #define ARASAN_VENDOR_ENHANCED_STROBE BIT(0) +/* DWC IP vendor area 1 pointer */ +#define DWCMSHC_P_VENDOR_AREA1 0xe8 +#define DWCMSHC_AREA1_MASK GENMASK(11, 0) +/* Offset inside the vendor area 1 */ +#define DWCMSHC_EMMC_CONTROL 0x2c +#define DWCMSHC_ENHANCED_STROBE BIT(8) + /* Rockchip specific Registers */ #define DWCMSHC_EMMC_DLL_CTRL 0x800 #define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1) @@ -284,6 +291,21 @@ static int rk3568_emmc_get_phy(struct udevice *dev) return 0; } +static int rk3568_set_enhanced_strobe(struct sdhci_host *host) +{ + u32 vendor; + int reg; + + reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK) + + DWCMSHC_EMMC_CONTROL; + + vendor = sdhci_readl(host, reg); + vendor |= DWCMSHC_ENHANCED_STROBE; + sdhci_writel(host, vendor, reg); + + return 0; +} + static int rockchip_sdhci_set_ios_post(struct sdhci_host *host) { struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); @@ -473,6 +495,7 @@ static const struct sdhci_data rk3568_data = { .emmc_set_clock = rk3568_sdhci_emmc_set_clock, .get_phy = rk3568_emmc_get_phy, .emmc_phy_init = rk3568_emmc_phy_init, + .set_enhanced_strobe = rk3568_set_enhanced_strobe, }; static const struct udevice_id sdhci_ids[] = {
On RK3568, a register bit must be set to enable Enhanced Strobe. However, it appears that the address of this register may differ from vendor to vendor and should be read from the underlying MMC IP. Let the Rockchip SDHCI driver read this address and set the relevant bit when Enhanced Strobe configuration is requested. This is mostly ported from Linux' Synopsys DWC MSHC driver which happens to be the underlying IP. (drivers/mmc/host/sdhci-of-dwcmshc.c in Linux tree). Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> --- Merely build-tested as I don't have a RK3568 board. drivers/mmc/rockchip_sdhci.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)