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[67.190.101.114]) by smtp.gmail.com with ESMTPSA id y61sm6778937ota.31.2021.07.25.09.14.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jul 2021 09:14:04 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Tom Rini , Simon Glass , Jagan Teki , Jagannadha Sutradharudu Teki Subject: [PATCH v6 3/5] spi: Add checks for OF_CONTROL Date: Sun, 25 Jul 2021 10:13:45 -0600 Message-Id: <20210725161347.457937-4-sjg@chromium.org> X-Mailer: git-send-email 2.32.0.432.gabb21c7263-goog In-Reply-To: <20210725161347.457937-1-sjg@chromium.org> References: <20210725161347.457937-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean This uclass requires OF_CONTROL to be enabled but some boards use it in SPL without doing that. Add a warning so that the maintainer can fix it. Expand the check in spi_post_probe() too. Signed-off-by: Simon Glass --- Changes in v6: - Add new patch for SPI flash drivers/spi/spi-uclass.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index d867b278064..2ae3e075993 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -176,11 +176,11 @@ static int spi_child_post_bind(struct udevice *dev) static int spi_post_probe(struct udevice *bus) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct dm_spi_bus *spi = dev_get_uclass_priv(bus); - spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0); -#endif + if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) + spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0); + #if defined(CONFIG_NEEDS_MANUAL_RELOC) struct dm_spi_ops *ops = spi_get_ops(bus); static int reloc_done; @@ -471,6 +471,16 @@ int spi_slave_of_to_plat(struct udevice *dev, struct dm_spi_slave_plat *plat) int mode = 0; int value; + /* + * This uclass requires OF_CONTROL but this is included on some boards + * that don't support it in SPL. Return an error so the board vendor + * can resolve this. + */ + if (!CONFIG_IS_ENABLED(OF_CONTROL)) { + log_err("SPI flash requires OF_CONTROL enabled"); + return -ENOSYS; + } + plat->cs = dev_read_u32_default(dev, "reg", -1); plat->max_hz = dev_read_u32_default(dev, "spi-max-frequency", SPI_DEFAULT_SPEED_HZ);