diff mbox series

[v2,4/6] MIPS: malta: add DT bindings for PCI host controller

Message ID 20210715185401.301211-5-daniel.schwierzeck@gmail.com
State Accepted
Commit 73be5636f43e6c0bf3988cc14ceb7a35ecaadc2e
Delegated to: Daniel Schwierzeck
Headers show
Series Convert MIPS Malta boards to PCI DM | expand

Commit Message

Daniel Schwierzeck July 15, 2021, 6:53 p.m. UTC 
Add DT binding for GT64120 and MSC01 PCI controllers. Only
GT64120 is enabled by default to support Qemu. The MSC01 node
will be dynamically enabled by Malta board code dependent
on the plugged core card.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---

(no changes since v1)

 arch/mips/dts/mti,malta.dts | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
diff mbox series

Patch

diff --git a/arch/mips/dts/mti,malta.dts b/arch/mips/dts/mti,malta.dts
index d339229c2a..ef47a340bb 100644
--- a/arch/mips/dts/mti,malta.dts
+++ b/arch/mips/dts/mti,malta.dts
@@ -29,4 +29,32 @@ 
 			u-boot,dm-pre-reloc;
 		};
 	};
+
+	pci0@1bd00000 {
+		compatible = "mips,pci-msc01";
+		device_type = "pci";
+		reg = <0x1bd00000 0x2000>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		bus-range = <0x0 0x0>;
+		ranges = <0x01000000 0 0x00000000 0x00000000 0 0x800000		/* I/O */
+			  0x02000000 0 0x10000000 0xb0000000 0 0x10000000	/* MEM */>;
+
+		status = "disabled";
+	};
+
+	pci0@1be00000 {
+		compatible = "marvell,pci-gt64120";
+		device_type = "pci";
+		reg = <0x1be00000 0x2000>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		bus-range = <0x0 0x0>;
+		ranges = <0x01000000 0 0x00000000 0x00000000 0 0x20000		/* I/O */
+			  0x02000000 0 0x10000000 0x10000000 0 0x8000000	/* MEM */>;
+
+		status = "okay";
+	};
 };