From patchwork Mon Jul 12 16:42:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Rini X-Patchwork-Id: 1504101 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GNqMG3RW8z9sRf for ; Tue, 13 Jul 2021 02:43:06 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A826882E41; Mon, 12 Jul 2021 18:42:39 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=konsulko.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 4DDF882DF1; Mon, 12 Jul 2021 18:42:38 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H2, SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-qk1-f182.google.com (mail-qk1-f182.google.com [209.85.222.182]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 2543A82DF1 for ; Mon, 12 Jul 2021 18:42:26 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=konsulko.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tom.rini@gmail.com Received: by mail-qk1-f182.google.com with SMTP id 9so18578635qkf.3 for ; Mon, 12 Jul 2021 09:42:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SOIf9RWBc6frefLgqYxzmM6JV6xWQ6QNNjuS2aGjOm4=; b=gOSNNj3xTcCuBsVPkXHjyPrHDwo72xdRI9KS9HfVkzt+Nba7S2UhdJcb8B8H+mBn5r RnLUCtF42SoI9uueD46Jg5fYdcWe3pwCImAdZ/Swy0HLl85OhmVsXuUFi7Fl3b5NkIIo 7FuYDUEcpbRtdE6TlwoTAqfhmzf5zrwYdjugfG5eTdVyaon3iBBGWhSlqvBddXMuk9Qi LUkitHDUCRWWV+09+oNxFDCsYX0hKdhsRZvVMuzm1ENM74cChiyE4cgofYxk+rsiA9kD zEeqGbS582/+iEXtI7yKfeJ89ojJkmsmKDSLC6X8YbQfv23VT8mfIYJNiWyLZgcxcxy2 Pzpw== X-Gm-Message-State: AOAM531J1unx6j1BY79nS/sRj1Ijqf4zEKahjNMa7ibeBtvLcSSovIb+ Bl4650P3FnqTf4jNUAffPGP4tqDuZxWS X-Google-Smtp-Source: ABdhPJxdu7fUQmS9Sjm9onf4wyw5FvTAIvkN5diHxEHEw2XQnSUcDR+cgAgIhDILtLjW9Y4kKccFUQ== X-Received: by 2002:a05:620a:1ef:: with SMTP id x15mr7206625qkn.369.1626108143983; Mon, 12 Jul 2021 09:42:23 -0700 (PDT) Received: from bill-the-cat.lan (2603-6081-7b01-cbda-8124-e22d-adbc-1eeb.res6.spectrum.com. [2603:6081:7b01:cbda:8124:e22d:adbc:1eeb]) by smtp.gmail.com with ESMTPSA id w18sm6705886qkp.57.2021.07.12.09.42.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jul 2021 09:42:23 -0700 (PDT) From: Tom Rini To: u-boot@lists.denx.de Cc: Angelo Durgehello , TsiChung Liew Subject: [PATCH 5/5] m68k: Remove M52277EVB board Date: Mon, 12 Jul 2021 12:42:14 -0400 Message-Id: <20210712164214.19847-5-trini@konsulko.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210712164214.19847-1-trini@konsulko.com> References: <20210712164214.19847-1-trini@konsulko.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. As this is also the last in family remove the related support as well. Cc: Angelo Durgehello Cc: TsiChung Liew Signed-off-by: Tom Rini --- arch/m68k/Kconfig | 9 - arch/m68k/dts/M52277EVB.dts | 25 -- arch/m68k/dts/M52277EVB_stmicro.dts | 22 -- arch/m68k/dts/Makefile | 2 - arch/m68k/dts/mcf5227x.dtsi | 48 --- arch/m68k/include/asm/cache.h | 2 +- arch/m68k/include/asm/immap.h | 28 -- arch/m68k/include/asm/immap_5227x.h | 237 ----------- arch/m68k/include/asm/m5227x.h | 546 -------------------------- board/freescale/m52277evb/Kconfig | 15 - board/freescale/m52277evb/MAINTAINERS | 7 - board/freescale/m52277evb/Makefile | 6 - board/freescale/m52277evb/README | 228 ----------- board/freescale/m52277evb/m52277evb.c | 94 ----- configs/M52277EVB_defconfig | 34 -- configs/M52277EVB_stmicro_defconfig | 36 -- include/configs/M52277EVB.h | 243 ------------ 17 files changed, 1 insertion(+), 1581 deletions(-) delete mode 100644 arch/m68k/dts/M52277EVB.dts delete mode 100644 arch/m68k/dts/M52277EVB_stmicro.dts delete mode 100644 arch/m68k/dts/mcf5227x.dtsi delete mode 100644 arch/m68k/include/asm/immap_5227x.h delete mode 100644 arch/m68k/include/asm/m5227x.h delete mode 100644 board/freescale/m52277evb/Kconfig delete mode 100644 board/freescale/m52277evb/MAINTAINERS delete mode 100644 board/freescale/m52277evb/Makefile delete mode 100644 board/freescale/m52277evb/README delete mode 100644 board/freescale/m52277evb/m52277evb.c delete mode 100644 configs/M52277EVB_defconfig delete mode 100644 configs/M52277EVB_stmicro_defconfig delete mode 100644 include/configs/M52277EVB.h diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 2d4714184149..1ab37cc9fc3d 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -113,18 +113,10 @@ config M54418 bool select MCF5441x -config M52277 - bool - select MCF5227x - choice prompt "Target select" optional -config TARGET_M52277EVB - bool "Support M52277EVB" - select M52277 - config TARGET_M5235EVB bool "Support M5235EVB" select M5235 @@ -191,7 +183,6 @@ source "board/BuS/eb_cpu5282/Kconfig" source "board/astro/mcf5373l/Kconfig" source "board/cobra5272/Kconfig" source "board/freescale/m5208evbe/Kconfig" -source "board/freescale/m52277evb/Kconfig" source "board/freescale/m5235evb/Kconfig" source "board/freescale/m5249evb/Kconfig" source "board/freescale/m5253demo/Kconfig" diff --git a/arch/m68k/dts/M52277EVB.dts b/arch/m68k/dts/M52277EVB.dts deleted file mode 100644 index a2210c88115f..000000000000 --- a/arch/m68k/dts/M52277EVB.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello - */ - -/dts-v1/; -/include/ "mcf5227x.dtsi" - -/ { - model = "Freescale M52277EVB"; - compatible = "fsl,M52277EVB"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&dspi0 { - status = "okay"; -}; diff --git a/arch/m68k/dts/M52277EVB_stmicro.dts b/arch/m68k/dts/M52277EVB_stmicro.dts deleted file mode 100644 index 5fd3ca5efd8e..000000000000 --- a/arch/m68k/dts/M52277EVB_stmicro.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello - */ - -/dts-v1/; -/include/ "mcf5227x.dtsi" - -/ { - model = "Freescale M52277_stmicro"; - compatible = "fsl,M52277_stmicro"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - diff --git a/arch/m68k/dts/Makefile b/arch/m68k/dts/Makefile index 49618e64fef6..fdd435bc345e 100644 --- a/arch/m68k/dts/Makefile +++ b/arch/m68k/dts/Makefile @@ -1,7 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -dtb-$(CONFIG_TARGET_M52277EVB) += M52277EVB.dtb \ - M52277EVB_stmicro.dtb dtb-$(CONFIG_TARGET_M5235EVB) += M5235EVB.dtb \ M5235EVB_Flash32.dtb dtb-$(CONFIG_TARGET_COBRA5272) += cobra5272.dtb diff --git a/arch/m68k/dts/mcf5227x.dtsi b/arch/m68k/dts/mcf5227x.dtsi deleted file mode 100644 index 8c95edddb650..000000000000 --- a/arch/m68k/dts/mcf5227x.dtsi +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello - */ - -/ { - compatible = "fsl,mcf5227x"; - - aliases { - serial0 = &uart0; - spi0 = &dspi0; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - uart0: uart@fc060000 { - compatible = "fsl,mcf-uart"; - reg = <0xfc060000 0x40>; - status = "disabled"; - }; - - uart1: uart@fc064000 { - compatible = "fsl,mcf-uart"; - reg = <0xfc064000 0x40>; - status = "disabled"; - }; - - uart2: uart@fc068000 { - compatible = "fsl,mcf-uart"; - reg = <0xfc068000 0x40>; - status = "disabled"; - }; - - dspi0: dspi@fc05c000 { - compatible = "fsl,mcf-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfc05c000 0x100>; - spi-max-frequency = <50000000>; - num-cs = <4>; - spi-mode = <0>; - status = "disabled"; - }; - }; -}; diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index 1c04d6df7c51..ceb462f438f2 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -10,7 +10,7 @@ #define __CACHE_H #if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \ - defined(CONFIG_MCF52x2) || defined(CONFIG_MCF5227x) + defined(CONFIG_MCF52x2) #define CONFIG_CF_V2 #endif diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index 81837a7c161b..02aa95aaf262 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -32,34 +32,6 @@ #define CONFIG_SYS_NUM_IRQS (128) #endif /* CONFIG_M520x */ -#ifdef CONFIG_M52277 -#include -#include - -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) - -#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) - -#ifdef CONFIG_LCD -#define CONFIG_SYS_LCD_BASE (MMAP_LCD) -#endif - -/* Timer */ -#ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) -#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) -#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) -#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (6) -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) -#endif - -#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) -#define CONFIG_SYS_NUM_IRQS (128) -#endif /* CONFIG_M52277 */ - #ifdef CONFIG_M5235 #include #include diff --git a/arch/m68k/include/asm/immap_5227x.h b/arch/m68k/include/asm/immap_5227x.h deleted file mode 100644 index 710d6f5c0ddf..000000000000 --- a/arch/m68k/include/asm/immap_5227x.h +++ /dev/null @@ -1,237 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * MCF5227x Internal Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#ifndef __IMMAP_5227X__ -#define __IMMAP_5227X__ - -/* Module Base Addresses */ -#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000) -#define MMAP_CAN (CONFIG_SYS_MBAR + 0x00020000) -#define MMAP_RTC (CONFIG_SYS_MBAR + 0x0003C000) -#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040010) -#define MMAP_SCM3 (CONFIG_SYS_MBAR + 0x00040070) -#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000) -#define MMAP_IACK (CONFIG_SYS_MBAR + 0x00054000) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000) -#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000) -#define MMAP_PWM (CONFIG_SYS_MBAR + 0x00090000) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00094000) -#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000) -#define MMAP_ADC (CONFIG_SYS_MBAR + 0x000A8000) -#define MMAP_LCD (CONFIG_SYS_MBAR + 0x000AC000) -#define MMAP_LCD_BGLUT (CONFIG_SYS_MBAR + 0x000AC800) -#define MMAP_LCD_GWLUT (CONFIG_SYS_MBAR + 0x000ACC00) -#define MMAP_USBHW (CONFIG_SYS_MBAR + 0x000B0000) -#define MMAP_USBCAPS (CONFIG_SYS_MBAR + 0x000B0100) -#define MMAP_USBEHCI (CONFIG_SYS_MBAR + 0x000B0140) -#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B01A0) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000) -#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000) - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Reset Controller Module (RCM) */ -typedef struct rcm { - u8 rcr; - u8 rsr; -} rcm_t; - -/* Chip Configuration Module (CCM) */ -typedef struct ccm { - u16 ccr; /* Chip Configuration (Rd-only) */ - u16 resv1; - u16 rcon; /* Reset Configuration (Rd-only) */ - u16 cir; /* Chip Identification (Rd-only) */ - u32 resv2; - u16 misccr; /* Miscellaneous Control */ - u16 cdr; /* Clock Divider */ - u16 uocsr; /* USB On-the-Go Controller Status */ - u16 resv4; - u16 sbfsr; /* Serial Boot Status */ - u16 sbfcr; /* Serial Boot Control */ -} ccm_t; - -typedef struct canex_ctrl { - can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */ - u32 res0[0x700]; /* 0x100 */ - can_msg_t rxim[16]; /* 0x800 Rx Individual Mask 0-15 */ -} canex_t; - -/* General Purpose I/O Module (GPIO) */ -typedef struct gpio { - /* Port Output Data Registers */ - u8 podr_be; /* 0x00 */ - u8 podr_cs; /* 0x01 */ - u8 podr_fbctl; /* 0x02 */ - u8 podr_i2c; /* 0x03 */ - u8 rsvd1; /* 0x04 */ - u8 podr_uart; /* 0x05 */ - u8 podr_dspi; /* 0x06 */ - u8 podr_timer; /* 0x07 */ - u8 podr_lcdctl; /* 0x08 */ - u8 podr_lcddatah; /* 0x09 */ - u8 podr_lcddatam; /* 0x0A */ - u8 podr_lcddatal; /* 0x0B */ - - /* Port Data Direction Registers */ - u8 pddr_be; /* 0x0C */ - u8 pddr_cs; /* 0x0D */ - u8 pddr_fbctl; /* 0x0E */ - u8 pddr_i2c; /* 0x0F */ - u8 rsvd2; /* 0x10 */ - u8 pddr_uart; /* 0x11 */ - u8 pddr_dspi; /* 0x12 */ - u8 pddr_timer; /* 0x13 */ - u8 pddr_lcdctl; /* 0x14 */ - u8 pddr_lcddatah; /* 0x15 */ - u8 pddr_lcddatam; /* 0x16 */ - u8 pddr_lcddatal; /* 0x17 */ - - /* Port Pin Data/Set Data Registers */ - u8 ppdsdr_be; /* 0x18 */ - u8 ppdsdr_cs; /* 0x19 */ - u8 ppdsdr_fbctl; /* 0x1A */ - u8 ppdsdr_i2c; /* 0x1B */ - u8 rsvd3; /* 0x1C */ - u8 ppdsdr_uart; /* 0x1D */ - u8 ppdsdr_dspi; /* 0x1E */ - u8 ppdsdr_timer; /* 0x1F */ - u8 ppdsdr_lcdctl; /* 0x20 */ - u8 ppdsdr_lcddatah; /* 0x21 */ - u8 ppdsdr_lcddatam; /* 0x22 */ - u8 ppdsdr_lcddatal; /* 0x23 */ - - /* Port Clear Output Data Registers */ - u8 pclrr_be; /* 0x24 */ - u8 pclrr_cs; /* 0x25 */ - u8 pclrr_fbctl; /* 0x26 */ - u8 pclrr_i2c; /* 0x27 */ - u8 rsvd4; /* 0x28 */ - u8 pclrr_uart; /* 0x29 */ - u8 pclrr_dspi; /* 0x2A */ - u8 pclrr_timer; /* 0x2B */ - u8 pclrr_lcdctl; /* 0x2C */ - u8 pclrr_lcddatah; /* 0x2D */ - u8 pclrr_lcddatam; /* 0x2E */ - u8 pclrr_lcddatal; /* 0x2F */ - - /* Pin Assignment Registers */ - u8 par_be; /* 0x30 */ - u8 par_cs; /* 0x31 */ - u8 par_fbctl; /* 0x32 */ - u8 par_i2c; /* 0x33 */ - u16 par_uart; /* 0x34 */ - u8 par_dspi; /* 0x36 */ - u8 par_timer; /* 0x37 */ - u8 par_lcdctl; /* 0x38 */ - u8 par_irq; /* 0x39 */ - u16 rsvd6; /* 0x3A - 0x3B */ - u32 par_lcdh; /* 0x3C */ - u32 par_lcdl; /* 0x40 */ - - /* Mode select control registers */ - u8 mscr_fb; /* 0x44 */ - u8 mscr_sdram; /* 0x45 */ - - u16 rsvd7; /* 0x46 - 0x47 */ - u8 dscr_dspi; /* 0x48 */ - u8 dscr_timer; /* 0x49 */ - u8 dscr_i2c; /* 0x4A */ - u8 dscr_lcd; /* 0x4B */ - u8 dscr_debug; /* 0x4C */ - u8 dscr_clkrst; /* 0x4D */ - u8 dscr_irq; /* 0x4E */ - u8 dscr_uart; /* 0x4F */ -} gpio_t; - -/* SDRAM Controller (SDRAMC) */ -typedef struct sdramc { - u32 sdmr; /* Mode/Extended Mode */ - u32 sdcr; /* Control */ - u32 sdcfg1; /* Configuration 1 */ - u32 sdcfg2; /* Chip Select */ - u8 resv0[0x100]; - u32 sdcs0; /* Mode/Extended Mode */ - u32 sdcs1; /* Mode/Extended Mode */ -} sdramc_t; - -/* Phase Locked Loop (PLL) */ -typedef struct pll { - u32 pcr; /* PLL Control */ - u32 psr; /* PLL Status */ -} pll_t; - -/* System Control Module register */ -typedef struct scm1 { - u32 mpr; /* 0x00 Master Privilege */ - u32 rsvd1[7]; - u32 pacra; /* 0x20 */ - u32 pacrb; /* 0x24 */ - u32 pacrc; /* 0x28 */ - u32 pacrd; /* 0x2C */ - u32 rsvd2[4]; - u32 pacre; /* 0x40 */ - u32 pacrf; /* 0x44 */ - u32 pacrg; /* 0x48 */ - u32 rsvd3; - u32 pacri; /* 0x50 */ -} scm1_t; - -typedef struct scm2_ctrl { - u8 res1[3]; /* 0x00 - 0x02 */ - u8 wcr; /* 0x03 wakeup control */ - u16 res2; /* 0x04 - 0x05 */ - u16 cwcr; /* 0x06 Core Watchdog Control */ - u8 res3[3]; /* 0x08 - 0x0A */ - u8 cwsr; /* 0x0B Core Watchdog Service */ - u8 res4[2]; /* 0x0C - 0x0D */ - u8 scmisr; /* 0x0F Interrupt Status */ - u32 res5; /* 0x20 */ - u32 bcr; /* 0x24 Burst Configuration */ -} scm2_t; - -typedef struct scm3_ctrl { - u32 cfadr; /* 0x00 Core Fault Address */ - u8 res7; /* 0x04 */ - u8 cfier; /* 0x05 Core Fault Interrupt Enable */ - u8 cfloc; /* 0x06 Core Fault Location */ - u8 cfatr; /* 0x07 Core Fault Attributes */ - u32 cfdtr; /* 0x08 Core Fault Data */ -} scm3_t; - -typedef struct rtcex { - u32 rsvd1[3]; - u32 gocu; - u32 gocl; -} rtcex_t; -#endif /* __IMMAP_5227X__ */ diff --git a/arch/m68k/include/asm/m5227x.h b/arch/m68k/include/asm/m5227x.h deleted file mode 100644 index 67c16e0b90f3..000000000000 --- a/arch/m68k/include/asm/m5227x.h +++ /dev/null @@ -1,546 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * MCF5227x Internal Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#ifndef __MCF5227X__ -#define __MCF5227X__ - -/* Interrupt Controller (INTC) */ -#define INT0_LO_RSVD0 (0) -#define INT0_LO_EPORT1 (1) -#define INT0_LO_EPORT4 (4) -#define INT0_LO_EPORT7 (7) -#define INT0_LO_EDMA_00 (8) -#define INT0_LO_EDMA_01 (9) -#define INT0_LO_EDMA_02 (10) -#define INT0_LO_EDMA_03 (11) -#define INT0_LO_EDMA_04 (12) -#define INT0_LO_EDMA_05 (13) -#define INT0_LO_EDMA_06 (14) -#define INT0_LO_EDMA_07 (15) -#define INT0_LO_EDMA_08 (16) -#define INT0_LO_EDMA_09 (17) -#define INT0_LO_EDMA_10 (18) -#define INT0_LO_EDMA_11 (19) -#define INT0_LO_EDMA_12 (20) -#define INT0_LO_EDMA_13 (21) -#define INT0_LO_EDMA_14 (22) -#define INT0_LO_EDMA_15 (23) -#define INT0_LO_EDMA_ERR (24) -#define INT0_LO_SCM_CWIC (25) -#define INT0_LO_UART0 (26) -#define INT0_LO_UART1 (27) -#define INT0_LO_UART2 (28) -#define INT0_LO_I2C (30) -#define INT0_LO_DSPI (31) -#define INT0_HI_DTMR0 (32) -#define INT0_HI_DTMR1 (33) -#define INT0_HI_DTMR2 (34) -#define INT0_HI_DTMR3 (35) -#define INT0_HI_SCMIR (62) -#define INT0_HI_RTC_ISR (63) - -#define INT1_HI_CAN_BOFFINT (1) -#define INT1_HI_CAN_ERRINT (3) -#define INT1_HI_CAN_BUF0I (4) -#define INT1_HI_CAN_BUF1I (5) -#define INT1_HI_CAN_BUF2I (6) -#define INT1_HI_CAN_BUF3I (7) -#define INT1_HI_CAN_BUF4I (8) -#define INT1_HI_CAN_BUF5I (9) -#define INT1_HI_CAN_BUF6I (10) -#define INT1_HI_CAN_BUF7I (11) -#define INT1_HI_CAN_BUF8I (12) -#define INT1_HI_CAN_BUF9I (13) -#define INT1_HI_CAN_BUF10I (14) -#define INT1_HI_CAN_BUF11I (15) -#define INT1_HI_CAN_BUF12I (16) -#define INT1_HI_CAN_BUF13I (17) -#define INT1_HI_CAN_BUF14I (18) -#define INT1_HI_CAN_BUF15I (19) -#define INT1_HI_PIT0_PIF (43) -#define INT1_HI_PIT1_PIF (44) -#define INT1_HI_USBOTG_STS (47) -#define INT1_HI_SSI_ISR (49) -#define INT1_HI_PWM_INT (50) -#define INT1_HI_LCDC_ISR (51) -#define INT1_HI_CCM_UOCSR (53) -#define INT1_HI_DSPI_EOQF (54) -#define INT1_HI_DSPI_TFFF (55) -#define INT1_HI_DSPI_TCF (56) -#define INT1_HI_DSPI_TFUF (57) -#define INT1_HI_DSPI_RFDF (58) -#define INT1_HI_DSPI_RFOF (59) -#define INT1_HI_DSPI_RFOF_TFUF (60) -#define INT1_HI_TOUCH_ADC (61) -#define INT1_HI_PLL_LOCKS (62) - -/********************************************************************* -* Reset Controller Module (RCM) -*********************************************************************/ - -/* Bit definitions and macros for RCR */ -#define RCM_RCR_FRCRSTOUT (0x40) -#define RCM_RCR_SOFTRST (0x80) - -/* Bit definitions and macros for RSR */ -#define RCM_RSR_LOL (0x01) -#define RCM_RSR_WDR_CORE (0x02) -#define RCM_RSR_EXT (0x04) -#define RCM_RSR_POR (0x08) -#define RCM_RSR_SOFT (0x20) - -/********************************************************************* -* Chip Configuration Module (CCM) -*********************************************************************/ - -/* Bit definitions and macros for CCR */ -#define CCM_CCR_DRAMSEL (0x0100) -#define CCM_CCR_CSC_UNMASK (0xFF3F) -#define CCM_CCR_CSC_FBCS5_CS4 (0x00C0) -#define CCM_CCR_CSC_FBCS5_A22 (0x0080) -#define CCM_CCR_CSC_FB_A23_A22 (0x0040) -#define CCM_CCR_LIMP (0x0020) -#define CCM_CCR_LOAD (0x0010) -#define CCM_CCR_BOOTPS_UNMASK (0xFFF3) -#define CCM_CCR_BOOTPS_PS16 (0x0008) -#define CCM_CCR_BOOTPS_PS8 (0x0004) -#define CCM_CCR_BOOTPS_PS32 (0x0000) -#define CCM_CCR_OSCMODE_OSCBYPASS (0x0002) - -/* Bit definitions and macros for RCON */ -#define CCM_RCON_CSC_UNMASK (0xFF3F) -#define CCM_RCON_CSC_FBCS5_CS4 (0x00C0) -#define CCM_RCON_CSC_FBCS5_A22 (0x0080) -#define CCM_RCON_CSC_FB_A23_A22 (0x0040) -#define CCM_RCON_LIMP (0x0020) -#define CCM_RCON_LOAD (0x0010) -#define CCM_RCON_BOOTPS_UNMASK (0xFFF3) -#define CCM_RCON_BOOTPS_PS16 (0x0008) -#define CCM_RCON_BOOTPS_PS8 (0x0004) -#define CCM_RCON_BOOTPS_PS32 (0x0000) -#define CCM_RCON_OSCMODE_OSCBYPASS (0x0002) - -/* Bit definitions and macros for CIR */ -#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6) -#define CCM_CIR_PRN(x) ((x) & 0x003F) -#define CCM_CIR_PIN_MCF52277 (0x0000) - -/* Bit definitions and macros for MISCCR */ -#define CCM_MISCCR_RTCSRC (0x4000) -#define CCM_MISCCR_USBPUE (0x2000) /* USB transceiver pull-up */ -#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */ - -#define CCM_MISCCR_BME (0x0800) /* Bus monitor ext en bit */ -#define CCM_MISCCR_BMT_65536 (0) -#define CCM_MISCCR_BMT_32768 (1) -#define CCM_MISCCR_BMT_16384 (2) -#define CCM_MISCCR_BMT_8192 (3) -#define CCM_MISCCR_BMT_4096 (4) -#define CCM_MISCCR_BMT_2048 (5) -#define CCM_MISCCR_BMT_1024 (6) -#define CCM_MISCCR_BMT_512 (7) - -#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */ -#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */ -#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */ -#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */ -#define CCM_MISCCR_LCDCHEN (0x0004) /* LCD Int CLK en */ -#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense pol */ -#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */ - -/* Bit definitions and macros for CDR */ -#define CCM_CDR_USBDIV(x) (((x)&0x0003)<<12) -#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clk div */ -#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clk div */ - -/* Bit definitions and macros for UOCSR */ -#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (rd-only) */ -#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (rd-only) */ -#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (rd-only) */ -#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor en (rd-only) */ -#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (rd-only) */ -#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */ -#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */ -#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */ -#define CCM_UOCSR_SEND (0x0010) /* Session end */ -#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */ -#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt en */ -#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down en */ - -/********************************************************************* -* General Purpose I/O Module (GPIO) -*********************************************************************/ -/* Bit definitions and macros for PAR_BE */ -#define GPIO_PAR_BE_UNMASK (0x0F) -#define GPIO_PAR_BE_BE3_BE3 (0x08) -#define GPIO_PAR_BE_BE3_GPIO (0x00) -#define GPIO_PAR_BE_BE2_BE2 (0x04) -#define GPIO_PAR_BE_BE2_GPIO (0x00) -#define GPIO_PAR_BE_BE1_BE1 (0x02) -#define GPIO_PAR_BE_BE1_GPIO (0x00) -#define GPIO_PAR_BE_BE0_BE0 (0x01) -#define GPIO_PAR_BE_BE0_GPIO (0x00) - -/* Bit definitions and macros for PAR_CS */ -#define GPIO_PAR_CS_CS3 (0x10) -#define GPIO_PAR_CS_CS2 (0x08) -#define GPIO_PAR_CS_CS1_FBCS1 (0x06) -#define GPIO_PAR_CS_CS1_SDCS1 (0x04) -#define GPIO_PAR_CS_CS1_GPIO (0x00) -#define GPIO_PAR_CS_CS0 (0x01) - -/* Bit definitions and macros for PAR_FBCTL */ -#define GPIO_PAR_FBCTL_OE (0x80) -#define GPIO_PAR_FBCTL_TA (0x40) -#define GPIO_PAR_FBCTL_RW (0x20) -#define GPIO_PAR_FBCTL_TS_UNMASK (0xE7) -#define GPIO_PAR_FBCTL_TS_FBTS (0x18) -#define GPIO_PAR_FBCTL_TS_DMAACK (0x10) -#define GPIO_PAR_FBCTL_TS_GPIO (0x00) - -/* Bit definitions and macros for PAR_FECI2C */ -#define GPIO_PAR_I2C_SCL_UNMASK (0xF3) -#define GPIO_PAR_I2C_SCL_SCL (0x0C) -#define GPIO_PAR_I2C_SCL_CANTXD (0x08) -#define GPIO_PAR_I2C_SCL_U2TXD (0x04) -#define GPIO_PAR_I2C_SCL_GPIO (0x00) - -#define GPIO_PAR_I2C_SDA_UNMASK (0xFC) -#define GPIO_PAR_I2C_SDA_SDA (0x03) -#define GPIO_PAR_I2C_SDA_CANRXD (0x02) -#define GPIO_PAR_I2C_SDA_U2RXD (0x01) -#define GPIO_PAR_I2C_SDA_GPIO (0x00) - -/* Bit definitions and macros for PAR_UART */ -#define GPIO_PAR_UART_U1CTS_UNMASK (0x3FFF) -#define GPIO_PAR_UART_U1CTS_U1CTS (0xC000) -#define GPIO_PAR_UART_U1CTS_SSIBCLK (0x8000) -#define GPIO_PAR_UART_U1CTS_LCDCLS (0x4000) -#define GPIO_PAR_UART_U1CTS_GPIO (0x0000) - -#define GPIO_PAR_UART_U1RTS_UNMASK (0xCFFF) -#define GPIO_PAR_UART_U1RTS_U1RTS (0x3000) -#define GPIO_PAR_UART_U1RTS_SSIFS (0x2000) -#define GPIO_PAR_UART_U1RTS_LCDPS (0x1000) -#define GPIO_PAR_UART_U1RTS_GPIO (0x0000) - -#define GPIO_PAR_UART_U1RXD_UNMASK (0xF3FF) -#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00) -#define GPIO_PAR_UART_U1RXD_SSIRXD (0x0800) -#define GPIO_PAR_UART_U1RXD_GPIO (0x0000) - -#define GPIO_PAR_UART_U1TXD_UNMASK (0xFCFF) -#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300) -#define GPIO_PAR_UART_U1TXD_SSITXD (0x0200) -#define GPIO_PAR_UART_U1TXD_GPIO (0x0000) - -#define GPIO_PAR_UART_U0CTS_UNMASK (0xFF3F) -#define GPIO_PAR_UART_U0CTS_U0CTS (0x00C0) -#define GPIO_PAR_UART_U0CTS_T1OUT (0x0080) -#define GPIO_PAR_UART_U0CTS_USBVBUSEN (0x0040) -#define GPIO_PAR_UART_U0CTS_GPIO (0x0000) - -#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFCF) -#define GPIO_PAR_UART_U0RTS_U0RTS (0x0030) -#define GPIO_PAR_UART_U0RTS_T1IN (0x0020) -#define GPIO_PAR_UART_U0RTS_USBVBUSOC (0x0010) -#define GPIO_PAR_UART_U0RTS_GPIO (0x0000) - -#define GPIO_PAR_UART_U0RXD_UNMASK (0xFFF3) -#define GPIO_PAR_UART_U0RXD_U0RXD (0x000C) -#define GPIO_PAR_UART_U0RXD_CANRX (0x0008) -#define GPIO_PAR_UART_U0RXD_GPIO (0x0000) - -#define GPIO_PAR_UART_U0TXD_UNMASK (0xFFFC) -#define GPIO_PAR_UART_U0TXD_U0TXD (0x0003) -#define GPIO_PAR_UART_U0TXD_CANTX (0x0002) -#define GPIO_PAR_UART_U0TXD_GPIO (0x0000) - -/* Bit definitions and macros for PAR_DSPI */ -#define GPIO_PAR_DSPI_PCS0_UNMASK (0x3F) -#define GPIO_PAR_DSPI_PCS0_PCS0 (0xC0) -#define GPIO_PAR_DSPI_PCS0_U2RTS (0x80) -#define GPIO_PAR_DSPI_PCS0_GPIO (0x00) -#define GPIO_PAR_DSPI_SIN_UNMASK (0xCF) -#define GPIO_PAR_DSPI_SIN_SIN (0x30) -#define GPIO_PAR_DSPI_SIN_U2RXD (0x20) -#define GPIO_PAR_DSPI_SIN_GPIO (0x00) -#define GPIO_PAR_DSPI_SOUT_UNMASK (0xF3) -#define GPIO_PAR_DSPI_SOUT_SOUT (0x0C) -#define GPIO_PAR_DSPI_SOUT_U2TXD (0x08) -#define GPIO_PAR_DSPI_SOUT_GPIO (0x00) -#define GPIO_PAR_DSPI_SCK_UNMASK (0xFC) -#define GPIO_PAR_DSPI_SCK_SCK (0x03) -#define GPIO_PAR_DSPI_SCK_U2CTS (0x02) -#define GPIO_PAR_DSPI_SCK_GPIO (0x00) - -/* Bit definitions and macros for PAR_TIMER */ -#define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F) -#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) -#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) -#define GPIO_PAR_TIMER_T3IN_SSIMCLK (0x40) -#define GPIO_PAR_TIMER_T3IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF) -#define GPIO_PAR_TIMER_T2IN_T2IN (0x30) -#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) -#define GPIO_PAR_TIMER_T2IN_DSPIPCS2 (0x10) -#define GPIO_PAR_TIMER_T2IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3) -#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) -#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) -#define GPIO_PAR_TIMER_T1IN_LCDCONTRAST (0x04) -#define GPIO_PAR_TIMER_T1IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC) -#define GPIO_PAR_TIMER_T0IN_T0IN (0x03) -#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) -#define GPIO_PAR_TIMER_T0IN_LCDREV (0x01) -#define GPIO_PAR_TIMER_T0IN_GPIO (0x00) - -/* Bit definitions and macros for GPIO_PAR_LCDCTL */ -#define GPIO_PAR_LCDCTL_ACDOE_UNMASK (0xE7) -#define GPIO_PAR_LCDCTL_ACDOE_ACDOE (0x18) -#define GPIO_PAR_LCDCTL_ACDOE_SPLSPR (0x10) -#define GPIO_PAR_LCDCTL_ACDOE_GPIO (0x00) -#define GPIO_PAR_LCDCTL_FLM_VSYNC (0x04) -#define GPIO_PAR_LCDCTL_LP_HSYNC (0x02) -#define GPIO_PAR_LCDCTL_LSCLK (0x01) - -/* Bit definitions and macros for PAR_IRQ */ -#define GPIO_PAR_IRQ_IRQ4_UNMASK (0xF3) -#define GPIO_PAR_IRQ_IRQ4_SSIINPCLK (0x0C) -#define GPIO_PAR_IRQ_IRQ4_DMAREQ0 (0x08) -#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00) -#define GPIO_PAR_IRQ_IRQ1_UNMASK (0xFC) -#define GPIO_PAR_IRQ_IRQ1_PCIINT (0x03) -#define GPIO_PAR_IRQ_IRQ1_USBCLKIN (0x02) -#define GPIO_PAR_IRQ_IRQ1_SSICLKIN (0x01) -#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00) - -/* Bit definitions and macros for GPIO_PAR_LCDH */ -#define GPIO_PAR_LCDH_LD17_UNMASK (0xFFFFF3FF) -#define GPIO_PAR_LCDH_LD17_LD17 (0x00000C00) -#define GPIO_PAR_LCDH_LD17_LD11 (0x00000800) -#define GPIO_PAR_LCDH_LD17_GPIO (0x00000000) - -#define GPIO_PAR_LCDH_LD16_UNMASK (0xFFFFFCFF) -#define GPIO_PAR_LCDH_LD16_LD16 (0x00000300) -#define GPIO_PAR_LCDH_LD16_LD10 (0x00000200) -#define GPIO_PAR_LCDH_LD16_GPIO (0x00000000) - -#define GPIO_PAR_LCDH_LD15_UNMASK (0xFFFFFF3F) -#define GPIO_PAR_LCDH_LD15_LD15 (0x000000C0) -#define GPIO_PAR_LCDH_LD15_LD9 (0x00000080) -#define GPIO_PAR_LCDH_LD15_GPIO (0x00000000) - -#define GPIO_PAR_LCDH_LD14_UNMASK (0xFFFFFFCF) -#define GPIO_PAR_LCDH_LD14_LD14 (0x00000030) -#define GPIO_PAR_LCDH_LD14_LD8 (0x00000020) -#define GPIO_PAR_LCDH_LD14_GPIO (0x00000000) - -#define GPIO_PAR_LCDH_LD13_UNMASK (0xFFFFFFF3) -#define GPIO_PAR_LCDH_LD13_LD13 (0x0000000C) -#define GPIO_PAR_LCDH_LD13_CANTX (0x00000008) -#define GPIO_PAR_LCDH_LD13_GPIO (0x00000000) - -#define GPIO_PAR_LCDH_LD12_UNMASK (0xFFFFFFFC) -#define GPIO_PAR_LCDH_LD12_LD12 (0x00000003) -#define GPIO_PAR_LCDH_LD12_CANRX (0x00000002) -#define GPIO_PAR_LCDH_LD12_GPIO (0x00000000) - -/* Bit definitions and macros for GPIO_PAR_LCDL */ -#define GPIO_PAR_LCDL_LD11_UNMASK (0x3FFFFFFF) -#define GPIO_PAR_LCDL_LD11_LD11 (0xC0000000) -#define GPIO_PAR_LCDL_LD11_LD7 (0x80000000) -#define GPIO_PAR_LCDL_LD11_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD10_UNMASK (0xCFFFFFFF) -#define GPIO_PAR_LCDL_LD10_LD10 (0x30000000) -#define GPIO_PAR_LCDL_LD10_LD6 (0x20000000) -#define GPIO_PAR_LCDL_LD10_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD9_UNMASK (0xF3FFFFFF) -#define GPIO_PAR_LCDL_LD9_LD9 (0x0C000000) -#define GPIO_PAR_LCDL_LD9_LD5 (0x08000000) -#define GPIO_PAR_LCDL_LD9_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD8_UNMASK (0xFCFFFFFF) -#define GPIO_PAR_LCDL_LD8_LD8 (0x03000000) -#define GPIO_PAR_LCDL_LD8_LD4 (0x02000000) -#define GPIO_PAR_LCDL_LD8_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD7_UNMASK (0xFF3FFFFF) -#define GPIO_PAR_LCDL_LD7_LD7 (0x00C00000) -#define GPIO_PAR_LCDL_LD7_PWM7 (0x00800000) -#define GPIO_PAR_LCDL_LD7_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD6_UNMASK (0xFFCFFFFF) -#define GPIO_PAR_LCDL_LD6_LD6 (0x00300000) -#define GPIO_PAR_LCDL_LD6_PWM5 (0x00200000) -#define GPIO_PAR_LCDL_LD6_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD5_UNMASK (0xFFF3FFFF) -#define GPIO_PAR_LCDL_LD5_LD5 (0x000C0000) -#define GPIO_PAR_LCDL_LD5_LD3 (0x00080000) -#define GPIO_PAR_LCDL_LD5_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD4_UNMASK (0xFFFCFFFF) -#define GPIO_PAR_LCDL_LD4_LD4 (0x00030000) -#define GPIO_PAR_LCDL_LD4_LD2 (0x00020000) -#define GPIO_PAR_LCDL_LD4_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD3_UNMASK (0xFFFF3FFF) -#define GPIO_PAR_LCDL_LD3_LD3 (0x0000C000) -#define GPIO_PAR_LCDL_LD3_LD1 (0x00008000) -#define GPIO_PAR_LCDL_LD3_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD2_UNMASK (0xFFFFCFFF) -#define GPIO_PAR_LCDL_LD2_LD2 (0x00003000) -#define GPIO_PAR_LCDL_LD2_LD0 (0x00002000) -#define GPIO_PAR_LCDL_LD2_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD1_UNMASK (0xFFFFF3FF) -#define GPIO_PAR_LCDL_LD1_LD1 (0x00000C00) -#define GPIO_PAR_LCDL_LD1_PWM3 (0x00000800) -#define GPIO_PAR_LCDL_LD1_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD0_UNMASK (0xFFFFFCFF) -#define GPIO_PAR_LCDL_LD0_LD0 (0x00000300) -#define GPIO_PAR_LCDL_LD0_PWM1 (0x00000200) -#define GPIO_PAR_LCDL_LD0_GPIO (0x00000000) - -/* Bit definitions and macros for MSCR_FB */ -#define GPIO_MSCR_FB_DUPPER_UNMASK (0xCF) -#define GPIO_MSCR_FB_DUPPER_25V_33V (0x30) -#define GPIO_MSCR_FB_DUPPER_FULL_18V (0x20) -#define GPIO_MSCR_FB_DUPPER_OD (0x10) -#define GPIO_MSCR_FB_DUPPER_HALF_18V (0x00) - -#define GPIO_MSCR_FB_DLOWER_UNMASK (0xF3) -#define GPIO_MSCR_FB_DLOWER_25V_33V (0x0C) -#define GPIO_MSCR_FB_DLOWER_FULL_18V (0x08) -#define GPIO_MSCR_FB_DLOWER_OD (0x04) -#define GPIO_MSCR_FB_DLOWER_HALF_18V (0x00) - -#define GPIO_MSCR_FB_ADDRCTL_UNMASK (0xFC) -#define GPIO_MSCR_FB_ADDRCTL_25V_33V (0x03) -#define GPIO_MSCR_FB_ADDRCTL_FULL_18V (0x02) -#define GPIO_MSCR_FB_ADDRCTL_OD (0x01) -#define GPIO_MSCR_FB_ADDRCTL_HALF_18V (0x00) - -/* Bit definitions and macros for MSCR_SDRAM */ -#define GPIO_MSCR_SDRAM_SDCLKB_UNMASK (0xCF) -#define GPIO_MSCR_SDRAM_SDCLKB_25V_33V (0x30) -#define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V (0x20) -#define GPIO_MSCR_SDRAM_SDCLKB_OD (0x10) -#define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V (0x00) - -#define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3) -#define GPIO_MSCR_SDRAM_SDCLK_25V_33V (0x0C) -#define GPIO_MSCR_SDRAM_SDCLK_FULL_18V (0x08) -#define GPIO_MSCR_SDRAM_SDCLK_OPD (0x04) -#define GPIO_MSCR_SDRAM_SDCLK_HALF_18V (0x00) - -#define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC) -#define GPIO_MSCR_SDRAM_SDCTL_25V_33V (0x03) -#define GPIO_MSCR_SDRAM_SDCTL_FULL_18V (0x02) -#define GPIO_MSCR_SDRAM_SDCTL_OPD (0x01) -#define GPIO_MSCR_SDRAM_SDCTL_HALF_18V (0x00) - -/* Bit definitions and macros for Drive Strength Control */ -#define DSCR_LOAD_50PF (0x03) -#define DSCR_LOAD_30PF (0x02) -#define DSCR_LOAD_20PF (0x01) -#define DSCR_LOAD_10PF (0x00) - -/********************************************************************* -* SDRAM Controller (SDRAMC) -*********************************************************************/ - -/* Bit definitions and macros for SDMR */ -#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */ -#define SDRAMC_SDMR_CMD (0x00010000) /* Command */ -#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */ -#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */ -#define SDRAMC_SDMR_BK_LMR (0x00000000) -#define SDRAMC_SDMR_BK_LEMR (0x40000000) - -/* Bit definitions and macros for SDCR */ -#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */ -#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */ -#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */ -#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */ -#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */ -#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */ -#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */ -#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */ -#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */ -#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */ -#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */ -#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */ -#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */ -#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000) - -/* Bit definitions and macros for SDCFG1 */ -#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */ -#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */ -#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */ -#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */ -#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */ -#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */ -#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */ - -/* Bit definitions and macros for SDCFG2 */ -#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */ -#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */ -#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */ -#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */ - -/* Bit definitions and macros for SDCS group */ -#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */ -#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ -#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) -#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000) -#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) -#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) -#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) -#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) -#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) -#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) -#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) -#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) -#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) -#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) -#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) -#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) -#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) - -/********************************************************************* -* Phase Locked Loop (PLL) -*********************************************************************/ - -/* Bit definitions and macros for PCR */ -#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */ -#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for bus/flexbus clock frequency */ -#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for SDRAM clock frequency */ -#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */ -#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */ -#define PLL_PCR_PFDR_MASK (0x000F0000) -#define PLL_PCR_OUTDIV5_MASK (0x000F0000) -#define PLL_PCR_OUTDIV3_MASK (0x00000F00) -#define PLL_PCR_OUTDIV2_MASK (0x000000F0) -#define PLL_PCR_OUTDIV1_MASK (0x0000000F) - -/* Bit definitions and macros for PSR */ -#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */ -#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */ -#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */ -#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */ - -/********************************************************************/ - -#endif /* __MCF5227X__ */ diff --git a/board/freescale/m52277evb/Kconfig b/board/freescale/m52277evb/Kconfig deleted file mode 100644 index c4278926a4ba..000000000000 --- a/board/freescale/m52277evb/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_M52277EVB - -config SYS_CPU - default "mcf5227x" - -config SYS_BOARD - default "m52277evb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "M52277EVB" - -endif diff --git a/board/freescale/m52277evb/MAINTAINERS b/board/freescale/m52277evb/MAINTAINERS deleted file mode 100644 index a2a2176f6a39..000000000000 --- a/board/freescale/m52277evb/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -M52277EVB BOARD -M: TsiChung Liew -S: Maintained -F: board/freescale/m52277evb/ -F: include/configs/M52277EVB.h -F: configs/M52277EVB_defconfig -F: configs/M52277EVB_stmicro_defconfig diff --git a/board/freescale/m52277evb/Makefile b/board/freescale/m52277evb/Makefile deleted file mode 100644 index f98b0c937762..000000000000 --- a/board/freescale/m52277evb/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = m52277evb.o diff --git a/board/freescale/m52277evb/README b/board/freescale/m52277evb/README deleted file mode 100644 index 8bfd8122dd89..000000000000 --- a/board/freescale/m52277evb/README +++ /dev/null @@ -1,228 +0,0 @@ -Freescale MCF52277EVB ColdFire Development Board -================================================ - -TsiChung Liew(Tsi-Chung.Liew@freescale.com) -Created Jan 8, 2008 -=========================================== - - -Changed files: -============== - -- board/freescale/m52277evb/m52277evb.c Dram setup -- board/freescale/m52277evb/Makefile Makefile -- board/freescale/m52277evb/config.mk config make -- board/freescale/m52277evb/u-boot.lds Linker description - -- arch/m68k/cpu/mcf5227x/cpu.c cpu specific code -- arch/m68k/cpu/mcf5227x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs -- arch/m68k/cpu/mcf5227x/interrupts.c cpu specific interrupt support -- arch/m68k/cpu/mcf5227x/speed.c system, flexbus, and cpu clock -- arch/m68k/cpu/mcf5227x/Makefile Makefile -- arch/m68k/cpu/mcf5227x/config.mk config make -- arch/m68k/cpu/mcf5227x/start.S start up assembly code - -- board/freescale/m52277evb/README This readme file - -- drivers/serial/mcfuart.c ColdFire common UART driver -- drivers/rtc/mcfrtc.c Realtime clock Driver - -- include/asm-m68k/bitops.h Bit operation function export -- include/asm-m68k/byteorder.h Byte order functions -- include/asm-m68k/crossbar.h CrossBar structure and definition -- include/asm-m68k/dspi.h DSPI structure and definition -- include/asm-m68k/edma.h eDMA structure and definition -- include/asm-m68k/flexbus.h FlexBus structure and definition -- include/asm-m68k/fsl_i2c.h I2C structure and definition -- include/asm-m68k/global_data.h Global data structure -- include/asm-m68k/immap.h ColdFire specific header file and driver macros -- include/asm-m68k/immap_5227x.h mcf5227x specific header file -- include/asm-m68k/io.h io functions -- include/asm-m68k/lcd.h LCD structure and definition -- include/asm-m68k/m5227x.h mcf5227x specific header file -- include/asm-m68k/posix_types.h Posix -- include/asm-m68k/processor.h header file -- include/asm-m68k/ptrace.h Exception structure -- include/asm-m68k/rtc.h Realtime clock header file -- include/asm-m68k/ssi.h SSI structure and definition -- include/asm-m68k/string.h String function export -- include/asm-m68k/timer.h Timer structure and definition -- include/asm-m68k/types.h Data types definition -- include/asm-m68k/uart.h Uart structure and definition -- include/asm-m68k/u-boot.h U-Boot structure - -- include/configs/M52277EVB.h Board specific configuration file - -- arch/m68k/lib/board.c board init function -- arch/m68k/lib/cache.c -- arch/m68k/lib/interrupts Coldfire common interrupt functions -- arch/m68k/lib/m68k_linux.c -- arch/m68k/lib/time.c Timer functions (Dma timer and PIT) -- arch/m68k/lib/traps.c Exception init code - -1 MCF52277 specific Options/Settings -==================================== -1.1 pre-loader is no longer suppoer in this coldfire family - -1.2 Configuration settings for M52277EVB Development Board -CONFIG_MCF5227x -- define for all MCF5227x CPUs -CONFIG_M52277 -- define for all Freescale MCF52277 CPUs - -CONFIG_MCFUART -- define to use common CF Uart driver -CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 -CONFIG_BAUDRATE -- define UART baudrate - -CONFIG_MCFRTC -- define to use common CF RTC driver -CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h -CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency -RTC_DEBUG -- define to show RTC debug message -CONFIG_CMD_DATE -- enable to use date feature in U-Boot - -CONFIG_MCFTMR -- define to use DMA timer - -CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver -CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged -CONFIG_SYS_I2C_SPEED -- define for I2C speed -CONFIG_SYS_I2C_SLAVE -- define for I2C slave address -CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset -CONFIG_SYS_IMMR -- define for MBAR offset - -CONFIG_SYS_MBAR -- define MBAR offset - -CONFIG_MONITOR_IS_IN_RAM -- Not support - -CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF52277 internal SRAM - -CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register -CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register -CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register - -CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base - -CONFIG_LCD and CONFIG_CMD_USB are not supported in this current U-Boot, -update will be provided at later time - -2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL -=========================================== -2.1. System memory map: - Flash: 0x00000000-0x3FFFFFFF (1024MB) - DDR: 0x40000000-0x7FFFFFFF (1024MB) - SRAM: 0x80000000-0x8FFFFFFF (256MB) - IP: 0xF0000000-0xFFFFFFFF (256MB) - -2.2. For the initial bringup, we adopted a consistent memory scheme between U-Boot and - linux kernel, you can customize it based on your system requirements: - Flash0: 0x00000000-0x00FFFFFF (16MB) - - DDR: 0x40000000-0x4FFFFFFF (64MB) - SRAM: 0x80000000-0x80007FFF (32KB) - IP: 0xFC000000-0xFC0FFFFF (64KB) - -3. COMPILATION -============== -3.1 To create U-Boot the gcc-4.1-xx compiler set (ColdFire ELF or -uClinux version) from codesourcery.com was used. Download it from: -http://www.codesourcery.com/gnu_toolchains/coldfire/download.html - -3.2 Compilation - export CROSS_COMPILE=cross-compile-prefix - cd u-boot-1.x.x - make distclean - make M52277EVB_config - make - -4. SCREEN DUMP -============== -4.1 M52277EVB Development board - (NOTE: May not show exactly the same) - -U-Boot 1.3.1 (Jan 8 2008 - 12:44:08) - -CPU: Freescale MCF52277 (Mask:6c Version:0) - CPU CLK 160 Mhz BUS CLK 80 Mhz FLB CLK 80 MHZ - INP CLK 16 Mhz VCO CLK 480 Mhz -Board: Freescale 52277 EVB -I2C: ready -DRAM: 64 MB -FLASH: 16 MB -In: serial -Out: serial -Err: serial --> print -baudrate=115200 -hostname=M52277EVB -inpclk=16000000 -loadaddr=(0x40000000 + 0x10000) -load=tftp ${loadaddr) ${u-boot} -upd=run load; run prog -prog=prot off 0 3ffff;era 0 3ffff;cp.b ${loadaddr} 0 ${filesize};save -u-boot=u-boot.bin -stdin=serial -stdout=serial -stderr=serial -mem=65024k - -Environment size: 280/32764 bytes --> bdinfo -memstart = 0x40000000 -memsize = 0x04000000 -flashstart = 0x00000000 -flashsize = 0x01000000 -flashoffset = 0x00000000 -sramstart = 0x80000000 -sramsize = 0x00008000 -mbar = 0xFC000000 -busfreq = 80 MHz -flbfreq = 80 Mhz -inpfreq = 16 Mhz -vcofreq = 480 Mhz - -baudrate = 115200 bps --> --> help -? - alias for 'help' -base - print or set address offset -bdinfo - print Board Info structure -boot - boot default, i.e., run 'bootcmd' -bootd - boot default, i.e., run 'bootcmd' -bootelf - Boot from an ELF image in memory -bootm - boot application image from memory -bootp - boot image via network using BootP/TFTP protocol -bootvx - Boot vxWorks from an ELF image -cmp - memory compare -coninfo - print console devices and information -cp - memory copy -crc32 - checksum calculation -date - get/set/reset date & time -dcache - enable or disable data cache -echo - echo args to console -erase - erase FLASH memory -flinfo - print FLASH memory information -go - start application at address 'addr' -help - print online help -i2c - I2C sub-system -icache - enable or disable instruction cache -iminfo - print header information for application image -imls - list all images found in flash -itest - return true/false on integer compare -loadb - load binary file over serial line (kermit mode) -loads - load S-Record file over serial line -loady - load binary file over serial line (ymodem mode) -loop - infinite loop on address range -ls - list files in a directory (default /) -md - memory display -mm - memory modify (auto-incrementing) -mtest - simple RAM test -mw - memory write (fill) -nm - memory modify (constant address) -ping - send ICMP ECHO_REQUEST to network host -printenv- print environment variables -protect - enable or disable FLASH write protection -reset - Perform RESET of the CPU -run - run commands in an environment variable -saveenv - save environment variables to persistent storage -setenv - set environment variables -sleep - delay execution for some time -source - run script from memory -version - print monitor version --> diff --git a/board/freescale/m52277evb/m52277evb.c b/board/freescale/m52277evb/m52277evb.c deleted file mode 100644 index 510af33e4c3c..000000000000 --- a/board/freescale/m52277evb/m52277evb.c +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - puts("Board: "); - puts("Freescale M52277 EVB\n"); - return 0; -}; - -int dram_init(void) -{ - u32 dramsize; - -#ifdef CONFIG_CF_SBF - /* - * Serial Boot: The dram is already initialized in start.S - * only require to return DRAM size - */ - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; -#else - sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); - gpio_t *gpio = (gpio_t *)(MMAP_GPIO); - u32 i; - - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; - - for (i = 0x13; i < 0x20; i++) { - if (dramsize == (1 << i)) - break; - } - i--; - - out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH); - - out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i); - - out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1); - out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2); - - /* Issue PALL */ - out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); - __asm__("nop"); - - /* Issue LEMR */ - out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE); - __asm__("nop"); - out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD); - __asm__("nop"); - - udelay(1000); - - /* Issue PALL */ - out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); - __asm__("nop"); - - /* Perform two refresh cycles */ - out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); - __asm__("nop"); - out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); - __asm__("nop"); - - out_be32(&sdram->sdcr, - (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); - - udelay(100); -#endif - gd->ram_size = dramsize; - - return 0; -}; - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf("DRAM test not implemented!\n"); - - return (0); -} diff --git a/configs/M52277EVB_defconfig b/configs/M52277EVB_defconfig deleted file mode 100644 index bab8ac4b78d2..000000000000 --- a/configs/M52277EVB_defconfig +++ /dev/null @@ -1,34 +0,0 @@ -CONFIG_M68K=y -CONFIG_SYS_TEXT_BASE=0x0 -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_SECT_SIZE=0x8000 -CONFIG_DEFAULT_DEVICE_TREE="M52277EVB" -CONFIG_TARGET_M52277EVB=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT" -CONFIG_BOOTDELAY=3 -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="-> " -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_JFFS2=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0x40000 -# CONFIG_NET is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_CF_SPI=y diff --git a/configs/M52277EVB_stmicro_defconfig b/configs/M52277EVB_stmicro_defconfig deleted file mode 100644 index 98c64ff31a66..000000000000 --- a/configs/M52277EVB_stmicro_defconfig +++ /dev/null @@ -1,36 +0,0 @@ -CONFIG_M68K=y -CONFIG_SYS_TEXT_BASE=0x43E00000 -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x30000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="M52277EVB_stmicro" -CONFIG_TARGET_M52277EVB=y -CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT" -CONFIG_BOOTDELAY=3 -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_JFFS2=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_USE_ENV_SPI_CS=y -CONFIG_ENV_SPI_CS=2 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -# CONFIG_NET is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_CF_SPI=y diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h deleted file mode 100644 index 0428be729b23..000000000000 --- a/include/configs/M52277EVB.h +++ /dev/null @@ -1,243 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Freescale MCF52277 EVB board. - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _M52277EVB_H -#define _M52277EVB_H - -#include - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) - -#undef CONFIG_WATCHDOG - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_HOSTNAME "M52277EVB" -#define CONFIG_SYS_UBOOT_END 0x3FFFF -#define CONFIG_SYS_LOAD_ADDR2 0x40010007 -#ifdef CONFIG_SYS_STMICRO_BOOT -/* ST Micro serial flash */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ - "loadaddr=0x40010000\0" \ - "uboot=u-boot.bin\0" \ - "load=loadb ${loadaddr} ${baudrate};" \ - "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ - "upd=run load; run prog\0" \ - "prog=sf probe 0:2 10000 1;" \ - "sf erase 0 30000;" \ - "sf write ${loadaddr} 0 30000;" \ - "save\0" \ - "" -#endif -#ifdef CONFIG_SYS_SPANSION_BOOT -#define CONFIG_EXTRA_ENV_SETTINGS \ - "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ - "loadaddr=0x40010000\0" \ - "uboot=u-boot.bin\0" \ - "load=loadb ${loadaddr} ${baudrate}\0" \ - "upd=run load; run prog\0" \ - "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ - " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ - "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ - __stringify(CONFIG_SYS_UBOOT_END) ";" \ - "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ - " ${filesize}; save\0" \ - "updsbf=run loadsbf; run progsbf\0" \ - "loadsbf=loadb ${loadaddr} ${baudrate};" \ - "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ - "progsbf=sf probe 0:2 10000 1;" \ - "sf erase 0 30000;" \ - "sf write ${loadaddr} 0 30000;" \ - "" -#endif - -/* LCD */ -#ifdef CONFIG_CMD_BMP -#define CONFIG_LCD_LOGO -#define CONFIG_SHARP_LQ035Q7DH06 -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 -#define CONFIG_SYS_USB_EHCI_CPU_INIT -#endif - -/* Realtime clock */ -#define CONFIG_MCFRTC -#undef RTC_DEBUG -#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) - -/* Timer */ -#define CONFIG_MCFTMR - -/* I2c */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR - -/* DSPI and Serial Flash */ -#define CONFIG_CF_DSPI -#define CONFIG_SYS_SBFHDR_SIZE 0x7 - -/* Input, PCI, Flexbus, and VCO */ -#define CONFIG_EXTRA_CLOCK - -#define CONFIG_SYS_INPUT_CLKSRC 16000000 - -#define CONFIG_PRAM 2048 /* 2048 KB */ - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) - -#define CONFIG_SYS_MBAR 0xFC000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/* - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) -#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x43711630 -#define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 -#define CONFIG_SYS_SDRAM_EMOD 0x81810000 -#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 -#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00 - -#ifdef CONFIG_CF_SBF -# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) -#else -# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#endif -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) - -/* - * Configuration for environment - * Environment is not embedded in u-boot. First time runing may have env - * crc error warning if there is no correct environment on the flash. - */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#ifdef CONFIG_SYS_STMICRO_BOOT -# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE -#endif -#ifdef CONFIG_SYS_SPANSION_BOOT -# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE -#endif - -#ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_FLASH_SPANSION_S29WS_N 1 -# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ -# define CONFIG_SYS_FLASH_CHECKSUM -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } -#endif - -#define LDS_BOARD_TEXT \ - arch/m68k/cpu/mcf5227x/built-in.o (.text*) \ - arch/m68k/lib/built-in.o (.text*) - -/* - * This is setting for JFFS2 support in u-boot. - * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. - */ -#ifdef CONFIG_CMD_JFFS2 -# define CONFIG_JFFS2_DEV "nor0" -# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000) -# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000) -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ - CF_CACR_DISD | CF_CACR_INVI | \ - CF_CACR_CEIB | CF_CACR_DCM | \ - CF_CACR_EUSP) - -/*----------------------------------------------------------------------- - * Memory bank definitions - */ -/* - * CS0 - NOR Flash - * CS1 - Available - * CS2 - Available - * CS3 - Available - * CS4 - Available - * CS5 - Available - */ - -#ifdef CONFIG_CF_SBF -#define CONFIG_SYS_CS0_BASE 0x04000000 -#define CONFIG_SYS_CS0_MASK 0x00FF0001 -#define CONFIG_SYS_CS0_CTRL 0x00001FA0 -#else -#define CONFIG_SYS_CS0_BASE 0x00000000 -#define CONFIG_SYS_CS0_MASK 0x00FF0001 -#define CONFIG_SYS_CS0_CTRL 0x00001FA0 -#endif - -#endif /* _M52277EVB_H */