Message ID | 20210616023326.18135-1-qianfanguijin@163.com |
---|---|
State | Changes Requested |
Delegated to: | Andre Przywara |
Headers | show |
Series | [1/4] phy-sun4i-usb: Fix sun8i_r40_cfg | expand |
On Wed, 16 Jun 2021 10:33:23 +0800 qianfanguijin@163.com (qianfanguijin@163.com) wrote: Hi, first many thanks for sending this! Indeed OTG support was broken/missing on the R40, also in Linux. So it seems you have the found the problem: the missing PHY multiplex. Many thanks for that! This indeed enables OTG functionality for me (although with some changes). That means that actually a similar patch needs to go through Linux. Do you plan on enabling support in Linux as well? > From: qianfan Zhao <qianfanguijin@163.com> > > The address of sun8i_r40's phyctrl is 0x01c13404, But this isn't quite right, is it? See below. > enable_pmu and dual_route. Ah, of course! The R40 is closer to the A33/A23 here, with not having separate EHCI0/OHCI0 controllers, instead relying on the MUSB host IP. So indeed we don't have the PHY multiplex for PHY0. I think this is the root cause of the non-working OTG support so far! > Signed-off-by: qianfan Zhao <qianfanguijin@163.com> > --- > drivers/phy/allwinner/phy-sun4i-usb.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c > index 5723c98032..608ba46242 100644 > --- a/drivers/phy/allwinner/phy-sun4i-usb.c > +++ b/drivers/phy/allwinner/phy-sun4i-usb.c > @@ -587,10 +587,10 @@ static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = { > .num_phys = 3, > .type = sun8i_r40_phy, > .disc_thresh = 3, > - .phyctl_offset = REG_PHYCTL_A33, > + .phyctl_offset = REG_PHYCTL_A10, So this doesn't work for me, no device appearing on the host. Also writing anything to this register (+0x04) reads back as 0, so it's not implemented, as in the H3. The register at +0x10 however works, and if I keep the A33 line, OTG indeed works for me. Same in Linux, btw. > .dedicated_clocks = true, > - .enable_pmu_unk1 = true, > - .phy0_dual_route = true, > + .enable_pmu_unk1 = false, > + .phy0_dual_route = false, If they are false, you don't need to list them, the default of 0 will take care of this. Cheers, Andre > }; > > static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
在 2021/6/21 8:33, Andre Przywara 写道: > On Wed, 16 Jun 2021 10:33:23 +0800 > qianfanguijin@163.com (qianfanguijin@163.com) wrote: > > Hi, > > first many thanks for sending this! Indeed OTG support was > broken/missing on the R40, also in Linux. > So it seems you have the found the problem: the missing PHY multiplex. > Many thanks for that! This indeed enables OTG functionality for me > (although with some changes). That means that actually a similar patch > needs to go through Linux. > Do you plan on enabling support in Linux as well? sure. >> From: qianfan Zhao <qianfanguijin@163.com> >> >> The address of sun8i_r40's phyctrl is 0x01c13404, > But this isn't quite right, is it? See below. Yes, the right address of R40 is 0x01c13410. I had checked the bsp code of allwinner: #if defined (CONFIG_ARCH_SUN50I) || defined (CONFIG_ARCH_SUN8IW10) || defined (CONFIG_ARCH_SUN8IW11)#define USBPHYC_REG_o_PHYCTL 0x0410#else#define USBPHYC_REG_o_PHYCTL 0x0404#endif But I had no idea why the addres 0x01c13404 can work fine, maybe I load u-boot by using sunxi-tools, that the usb otg is already init by IBR. >> enable_pmu and dual_route. > Ah, of course! The R40 is closer to the A33/A23 here, with not having > separate EHCI0/OHCI0 controllers, instead relying on the MUSB host IP. > So indeed we don't have the PHY multiplex for PHY0. > I think this is the root cause of the non-working OTG support so far! > >> Signed-off-by: qianfan Zhao <qianfanguijin@163.com> >> --- >> drivers/phy/allwinner/phy-sun4i-usb.c | 6 +++--- >> 1 file changed, 3 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c >> index 5723c98032..608ba46242 100644 >> --- a/drivers/phy/allwinner/phy-sun4i-usb.c >> +++ b/drivers/phy/allwinner/phy-sun4i-usb.c >> @@ -587,10 +587,10 @@ static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = { >> .num_phys = 3, >> .type = sun8i_r40_phy, >> .disc_thresh = 3, >> - .phyctl_offset = REG_PHYCTL_A33, >> + .phyctl_offset = REG_PHYCTL_A10, > So this doesn't work for me, no device appearing on the host. Also > writing anything to this register (+0x04) reads back as 0, so it's not > implemented, as in the H3. The register at +0x10 however works, and if I > keep the A33 line, OTG indeed works for me. Same in Linux, btw. > >> .dedicated_clocks = true, >> - .enable_pmu_unk1 = true, >> - .phy0_dual_route = true, >> + .enable_pmu_unk1 = false, >> + .phy0_dual_route = false, > If they are false, you don't need to list them, the default of 0 will > take care of this. Thanks for yours guide, I will make a change later. > > Cheers, > Andre > >> }; >> >> static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index 5723c98032..608ba46242 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -587,10 +587,10 @@ static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = { .num_phys = 3, .type = sun8i_r40_phy, .disc_thresh = 3, - .phyctl_offset = REG_PHYCTL_A33, + .phyctl_offset = REG_PHYCTL_A10, .dedicated_clocks = true, - .enable_pmu_unk1 = true, - .phy0_dual_route = true, + .enable_pmu_unk1 = false, + .phy0_dual_route = false, }; static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {