| Message ID | 20210615153735.26808-3-a-govindraju@ti.com |
|---|---|
| State | Superseded |
| Delegated to: | Lokesh Vutla |
| Headers | show |
| Series | AM64: Update the locations of various elements in SRAM | expand |
diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi index 9c04690e410a..9c4b3cd2a98f 100644 --- a/arch/arm/dts/k3-am64-main.dtsi +++ b/arch/arm/dts/k3-am64-main.dtsi @@ -16,6 +16,14 @@ tfa-sram@1c4000 { reg = <0x1c4000 0x1c000>; }; + + dmsc-sram@1e0000 { + reg = <0x1e0000 0x1c000>; + }; + + sproxy-sram@1fc000 { + reg = <0x1fc000 0x4000>; + }; }; gic500: interrupt-controller@1800000 {
The final 128KB in SRAM is reserved by default for DMSC-lite code and secure proxy communication buffer. The memory region used for DMSC-lite code can be optionally freed up by secure firmware API[1]. However, the buffer for secure proxy communication is not configurable. This default hardware configuration is unique for AM64. Therefore, indicate the area reserved for DMSC-lite code and secure proxy communication buffer in the oc_sram device tree node. [1] - http://downloads.ti.com/tisci/esd/latest/6_topic_user_guides/security_handover.html#triggering-security-handover Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> --- arch/arm/dts/k3-am64-main.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)