diff mbox series

[RESEND,3/6] clk: imx8mm: Add SPI clocks

Message ID 20210607123707.189163-4-frieder@fris.de
State Awaiting Upstream
Delegated to: Stefano Babic
Headers show
Series Add support for Kontron i.MX6UL/ULL and i.MX8MM modules/boards | expand

Commit Message

Frieder Schrempf June 7, 2021, 12:36 p.m. UTC 
From: Frieder Schrempf <frieder.schrempf@kontron.de>

Add the clocks for the ECSPI controllers. This is ported from
Linux v5.13-rc4.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
---
 drivers/clk/imx/clk-imx8mm.c | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

Comments

Stefano Babic July 10, 2021, 3:52 p.m. UTC | #1 
> From: Frieder Schrempf <frieder.schrempf@kontron.de>
> Add the clocks for the ECSPI controllers. This is ported from
> Linux v5.13-rc4.
> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic
Stefano Babic July 10, 2021, 7:34 p.m. UTC | #2 
> From: Frieder Schrempf <frieder.schrempf@kontron.de>
> Add the clocks for the ECSPI controllers. This is ported from
> Linux v5.13-rc4.
> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic
diff mbox series

Patch

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index d32ff8409a..3aa8c641f9 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -131,6 +131,15 @@  static const char *imx8mm_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "
 static const char *imx8mm_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m",
 					     "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
 
+static const char *imx8mm_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
+					   "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
+
+static const char *imx8mm_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
+					   "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
+
+static const char *imx8mm_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
+					   "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
+
 static ulong imx8mm_clk_get_rate(struct clk *clk)
 {
 	struct clk *c;
@@ -393,7 +402,19 @@  static int imx8mm_clk_probe(struct udevice *dev)
 		imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100));
 	clk_dm(IMX8MM_CLK_USB_PHY_REF,
 		imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180));
-
+	clk_dm(IMX8MM_CLK_ECSPI1,
+	       imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280));
+	clk_dm(IMX8MM_CLK_ECSPI2,
+	       imx8m_clk_composite("ecspi2", imx8mm_ecspi2_sels, base + 0xb300));
+	clk_dm(IMX8MM_CLK_ECSPI3,
+	       imx8m_clk_composite("ecspi3", imx8mm_ecspi3_sels, base + 0xc180));
+
+	clk_dm(IMX8MM_CLK_ECSPI1_ROOT,
+	       imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
+	clk_dm(IMX8MM_CLK_ECSPI2_ROOT,
+	       imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
+	clk_dm(IMX8MM_CLK_ECSPI3_ROOT,
+	       imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
 	clk_dm(IMX8MM_CLK_I2C1_ROOT,
 	       imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
 	clk_dm(IMX8MM_CLK_I2C2_ROOT,