| Message ID | 20210511120412.25065-1-bmeng.cn@gmail.com |
|---|---|
| State | Accepted |
| Commit | a6d7e8c9149f5f1b94f68129fbe5dec9e1e1489d |
| Delegated to: | Andes |
| Headers | show |
| Series | riscv: Split SiFive CLINT support between SPL and U-Boot proper | expand |
On 5/11/21 8:04 AM, Bin Meng wrote: > At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to > control the enabling of SiFive CLINT support in both SPL (M-mode) > and U-Boot proper (S-mode). So for a typical SPL config that the > SiFive CLINT driver is enabled in both SPL and U-Boot proper, that > means the S-mode U-Boot tries to access the memory-mapped CLINT > registers directly, instead of the normal 'rdtime' instruction. > > This was not a problem before, as the hardware does not forbid the > access from S-mode. However this becomes an issue now with OpenSBI > commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") > that the SiFive CLINT register space is protected by PMP for M-mode > access only. U-Boot proper does not boot any more with the latest > OpenSBI, that access exceptions are fired forever from U-Boot when > trying to read the timer value via the SiFive CLINT driver in U-Boot. > > To solve this, we need to split current SiFive CLINT support between > SPL and U-Boot proper, using 2 separate Kconfig options. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> > --- > > arch/riscv/Kconfig | 9 ++++++++- > arch/riscv/cpu/fu540/Kconfig | 2 +- > arch/riscv/cpu/generic/Kconfig | 3 ++- > arch/riscv/include/asm/global_data.h | 2 +- > arch/riscv/lib/Makefile | 2 +- > drivers/timer/Makefile | 2 +- > 6 files changed, 14 insertions(+), 6 deletions(-) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 3f221dccdb..82e10da11e 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -158,7 +158,14 @@ config DMA_ADDR_T_64BIT > > config SIFIVE_CLINT > bool > - depends on RISCV_MMODE || SPL_RISCV_MMODE > + depends on RISCV_MMODE > + help > + The SiFive CLINT block holds memory-mapped control and status registers > + associated with software and timer interrupts. > + > +config SPL_SIFIVE_CLINT > + bool > + depends on SPL_RISCV_MMODE > help > The SiFive CLINT block holds memory-mapped control and status registers > associated with software and timer interrupts. > diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig > index 616b25650f..dcf099447b 100644 > --- a/arch/riscv/cpu/fu540/Kconfig > +++ b/arch/riscv/cpu/fu540/Kconfig > @@ -11,7 +11,7 @@ config SIFIVE_FU540 > imply CPU > imply CPU_RISCV > imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) > - imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE) > + imply SPL_SIFIVE_CLINT > imply CMD_CPU > imply SPL_CPU > imply SPL_OPENSBI > diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig > index a4934bb957..e025134b23 100644 > --- a/arch/riscv/cpu/generic/Kconfig > +++ b/arch/riscv/cpu/generic/Kconfig > @@ -9,7 +9,8 @@ config GENERIC_RISCV > imply CPU > imply CPU_RISCV > imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) > - imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE) > + imply SIFIVE_CLINT if RISCV_MMODE > + imply SPL_SIFIVE_CLINT if SPL_RISCV_MMODE > imply CMD_CPU > imply SPL_CPU > imply SPL_OPENSBI > diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h > index d3a0b1d221..095484a635 100644 > --- a/arch/riscv/include/asm/global_data.h > +++ b/arch/riscv/include/asm/global_data.h > @@ -18,7 +18,7 @@ > struct arch_global_data { > long boot_hart; /* boot hart id */ > phys_addr_t firmware_fdt_addr; > -#ifdef CONFIG_SIFIVE_CLINT > +#if CONFIG_IS_ENABLED(SIFIVE_CLINT) > void __iomem *clint; /* clint base address */ > #endif > #ifdef CONFIG_ANDES_PLIC > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile > index d08cbe9b79..c4cc41434b 100644 > --- a/arch/riscv/lib/Makefile > +++ b/arch/riscv/lib/Makefile > @@ -11,7 +11,7 @@ obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o > obj-$(CONFIG_CMD_GO) += boot.o > obj-y += cache.o > ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y) > -obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o > +obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o > obj-$(CONFIG_ANDES_PLIC) += andes_plic.o > else > obj-$(CONFIG_SBI) += sbi.o > diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile > index eb5c48cc6c..2ebdeab0ce 100644 > --- a/drivers/timer/Makefile > +++ b/drivers/timer/Makefile > @@ -19,7 +19,7 @@ obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o > obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o > obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o > obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o > -obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint_timer.o > +obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o > obj-$(CONFIG_STI_TIMER) += sti-timer.o > obj-$(CONFIG_STM32_TIMER) += stm32_timer.o > obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o > Reviewed-by: Sean Anderson <seanga2@gmail.com>
> From: Bin Meng <bmeng.cn@gmail.com> > Sent: Tuesday, May 11, 2021 8:04 PM > To: Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; Sean Anderson <seanga2@gmail.com>; u-boot@lists.denx.de > Cc: Anup Patel <anup.patel@wdc.com>; Bin Meng <bmeng.cn@gmail.com> > Subject: [PATCH] riscv: Split SiFive CLINT support between SPL and U-Boot proper > > At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. > > This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. > > To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> > --- > > arch/riscv/Kconfig | 9 ++++++++- > arch/riscv/cpu/fu540/Kconfig | 2 +- > arch/riscv/cpu/generic/Kconfig | 3 ++- > arch/riscv/include/asm/global_data.h | 2 +- > arch/riscv/lib/Makefile | 2 +- > drivers/timer/Makefile | 2 +- > 6 files changed, 14 insertions(+), 6 deletions(-) Reviewed-by: Rick Chen <rick@andestech.com>
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 3f221dccdb..82e10da11e 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -158,7 +158,14 @@ config DMA_ADDR_T_64BIT config SIFIVE_CLINT bool - depends on RISCV_MMODE || SPL_RISCV_MMODE + depends on RISCV_MMODE + help + The SiFive CLINT block holds memory-mapped control and status registers + associated with software and timer interrupts. + +config SPL_SIFIVE_CLINT + bool + depends on SPL_RISCV_MMODE help The SiFive CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig index 616b25650f..dcf099447b 100644 --- a/arch/riscv/cpu/fu540/Kconfig +++ b/arch/riscv/cpu/fu540/Kconfig @@ -11,7 +11,7 @@ config SIFIVE_FU540 imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) - imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE) + imply SPL_SIFIVE_CLINT imply CMD_CPU imply SPL_CPU imply SPL_OPENSBI diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig index a4934bb957..e025134b23 100644 --- a/arch/riscv/cpu/generic/Kconfig +++ b/arch/riscv/cpu/generic/Kconfig @@ -9,7 +9,8 @@ config GENERIC_RISCV imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) - imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE) + imply SIFIVE_CLINT if RISCV_MMODE + imply SPL_SIFIVE_CLINT if SPL_RISCV_MMODE imply CMD_CPU imply SPL_CPU imply SPL_OPENSBI diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index d3a0b1d221..095484a635 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -18,7 +18,7 @@ struct arch_global_data { long boot_hart; /* boot hart id */ phys_addr_t firmware_fdt_addr; -#ifdef CONFIG_SIFIVE_CLINT +#if CONFIG_IS_ENABLED(SIFIVE_CLINT) void __iomem *clint; /* clint base address */ #endif #ifdef CONFIG_ANDES_PLIC diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index d08cbe9b79..c4cc41434b 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -11,7 +11,7 @@ obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y) -obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o +obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o obj-$(CONFIG_ANDES_PLIC) += andes_plic.o else obj-$(CONFIG_SBI) += sbi.o diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index eb5c48cc6c..2ebdeab0ce 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -19,7 +19,7 @@ obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o -obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint_timer.o +obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o obj-$(CONFIG_STI_TIMER) += sti-timer.o obj-$(CONFIG_STM32_TIMER) += stm32_timer.o obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o
At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- arch/riscv/Kconfig | 9 ++++++++- arch/riscv/cpu/fu540/Kconfig | 2 +- arch/riscv/cpu/generic/Kconfig | 3 ++- arch/riscv/include/asm/global_data.h | 2 +- arch/riscv/lib/Makefile | 2 +- drivers/timer/Makefile | 2 +- 6 files changed, 14 insertions(+), 6 deletions(-)