| Message ID | 20210510122341.13798-11-bmeng.cn@gmail.com |
|---|---|
| State | Accepted |
| Commit | 18cb82c35c764eccc3717260812c03323c324468 |
| Delegated to: | Andes |
| Headers | show |
| Series | riscv: Switch to use binman to generate u-boot.itb | expand |
On Mon, 10 May 2021 at 06:24, Bin Meng <bmeng.cn@gmail.com> wrote: > > Sort the RISC-V DTS build targets by their Kconfig target names in > alphabetical order. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> > > --- > > (no changes since v2) > > Changes in v2: > - new patch: "riscv: dts: Sort build targets in alphabetical order" > > arch/riscv/dts/Makefile | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Simon Glass <sjg@chromium.org> (as I have not seen anyone review this patch through several revisions...who is the maintainer?)
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 8138d89d84..3780334875 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb -dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb targets += $(dtb-y)
Sort the RISC-V DTS build targets by their Kconfig target names in alphabetical order. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- (no changes since v2) Changes in v2: - new patch: "riscv: dts: Sort build targets in alphabetical order" arch/riscv/dts/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)