| Message ID | 20210413155417.14433-1-michael@walle.cc |
|---|---|
| State | Accepted |
| Commit | 2bf4658b8c5e5f4f43dc1888fe39ea61e6eeba64 |
| Delegated to: | Priyanka Jain |
| Headers | show |
| Series | board: sl28: fix RGMII clock and voltage | expand |
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts index fe708bdbfa..33d85ed83a 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts @@ -41,8 +41,9 @@ qca,clk-out-frequency = <125000000>; qca,clk-out-strength = <AR803X_STRENGTH_FULL>; + qca,keep-pll-enabled; - vddio-supply = <&vddh>; + vddio-supply = <&vddio>; vddio: vddio-regulator { regulator-name = "VDDIO"; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts index 33b16303ad..b95e082b70 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts @@ -32,8 +32,9 @@ qca,clk-out-frequency = <125000000>; qca,clk-out-strength = <AR803X_STRENGTH_FULL>; + qca,keep-pll-enabled; - vddio-supply = <&vddh>; + vddio-supply = <&vddio>; vddio: vddio-regulator { regulator-name = "VDDIO";
It was noticed that the clock isn't continuously enabled when there is no link. This is because the 125MHz clock is derived from the internal PLL which seems to go into some kind of power-down mode every once in a while. The LS1028A expects a contiuous clock. Thus enable the PLL all the time. Also, the RGMII pad voltage is wrong, it was configured to 2.5V (that is the VDDH regulator). The correct voltage is 1.8V, i.e. the VDDIO regulator. Signed-off-by: Michael Walle <michael@walle.cc> --- arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts | 3 ++- arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-)