From patchwork Sun Apr 11 16:28:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 1464883 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=Vo7NP6jc; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FJHW171Nhz9rx6 for ; Mon, 12 Apr 2021 02:33:49 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D727C817B4; Sun, 11 Apr 2021 18:32:40 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1618158761; bh=LEjzI7EacuUN7zOfh2H7BWfITZRKNZVTed9EwqmhTgQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=Vo7NP6jcUhpxhTykqQShKQH6YLlXK97ae1zBkj05k4ZtjovLJSjwT3xesYOw7U+Px hsXTEYgeYEJUde4PBh7faCXqLXvAkOkuIJgFNCGnxF5SSY4uDLU7QHVYH1aozLYfG7 MGacKFIjizZMVpAHE82fyBVUSWoYk+TMmAnCa00KzaDV3mdG4xhWU7W9qiA0KvP8Vr 2iOVjqYVodzZicpogHMtjQqk5pFXzXy4cZWbflXHN4sZazfHnGGUir/awpZ+1GTrzT HXeJoFIOVpjihNwiz18JEPlIQzrppCKXBi0RPfu0LKIyAg3xLfkndF2mOllOlAl+TV D+abNCx6djj2g== Received: by phobos.denx.de (Postfix, from userid 109) id 0FF4A8175D; Sun, 11 Apr 2021 18:30:17 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-out.m-online.net (mail-out.m-online.net [IPv6:2001:a60:0:28:0:1:25:1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6425D80C6D for ; Sun, 11 Apr 2021 18:29:39 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=marex@denx.de Received: from frontend01.mail.m-online.net (unknown [192.168.8.182]) by mail-out.m-online.net (Postfix) with ESMTP id 4FJHQB6QSTz1s1VK; Sun, 11 Apr 2021 18:29:38 +0200 (CEST) Received: from localhost (dynscan1.mnet-online.de [192.168.6.70]) by mail.m-online.net (Postfix) with ESMTP id 4FJHQB69v8z1qqw9; Sun, 11 Apr 2021 18:29:38 +0200 (CEST) Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id SRqo1V4SnWNJ; Sun, 11 Apr 2021 18:29:37 +0200 (CEST) X-Auth-Info: nsKZg5YS5WvgwCfrDk632Ctg7cFmCox9c/6hDrBghqw= Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA; Sun, 11 Apr 2021 18:29:37 +0200 (CEST) From: Marek Vasut To: u-boot@lists.denx.de Cc: Marek Vasut , Fabio Estevam , Peng Fan , Stefano Babic , Ye Li , uboot-imx Subject: [PATCH V2 16/24] usb: ehci-mx6: Split usb_power_config() Date: Sun, 11 Apr 2021 18:28:53 +0200 Message-Id: <20210411162901.7238-16-marex@denx.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210411162901.7238-1-marex@denx.de> References: <20210411162901.7238-1-marex@denx.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Split usb_power_config() per SoC and pass in USB PHY, USBNC and ANATOP addresses instead of ad-hoc sequence numbers. This is only applicable on legacy systems which do not implement proper PHY support. Once PHY support is available, parts of this can be removed altogether and moved to the PHY driver, similar to Linux phy-mxs-usb.c . Fixes: 4de51cc25b5 ("usb: ehci-mx6: Drop assignment of sequence number") Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic Cc: Ye Li Cc: uboot-imx --- V2: - Always call usb_oc_config(), independent of whether CONFIG_PHY is or is not enabled - Only call usb_internal_phy_clock_gate() and usb_phy_enable() if CONFIG_PHY is disabled - Always define usb_power_config_*() and mark the empty implementations with __maybe_unused, since this vastly simplifies the ifdeffery and makes it much clearer what the intention of the ifdefs is --- drivers/usb/host/ehci-mx6.c | 143 +++++++++++++++++++++++------------- 1 file changed, 92 insertions(+), 51 deletions(-) diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index b43c55765c..d022df04ab 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -86,43 +86,18 @@ struct usbnc_regs { u32 adp_status; }; -#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) -static const unsigned phy_bases[] = { - USB_PHY0_BASE_ADDR, -#if defined(USB_PHY1_BASE_ADDR) - USB_PHY1_BASE_ADDR, -#endif -}; - -static void usb_internal_phy_clock_gate(void __iomem *phy_reg, int on) +#if defined(CONFIG_MX6) && !defined(CONFIG_PHY) +static void usb_power_config_mx6(struct anatop_regs __iomem *anatop, + int anatop_bits_index) { - phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET; - writel(USBPHY_CTRL_CLKGATE, phy_reg); -} - -static void usb_power_config(int index) -{ -#if defined(CONFIG_MX7ULP) - struct usbphy_regs __iomem *usbphy = - (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR; - - if (index > 0) - return; - - writel(ANADIG_USB2_CHRG_DETECT_EN_B | - ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B, - &usbphy->usb1_chrg_detect); - - scg_enable_usb_pll(true); - -#else - struct anatop_regs __iomem *anatop = - (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; void __iomem *chrg_detect; void __iomem *pll_480_ctrl_clr; void __iomem *pll_480_ctrl_set; - switch (index) { + if (!is_mx6()) + return; + + switch (anatop_bits_index) { case 0: chrg_detect = &anatop->usb1_chrg_detect; pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr; @@ -155,8 +130,61 @@ static void usb_power_config(int index) ANADIG_USB2_PLL_480_CTRL_POWER | ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS, pll_480_ctrl_set); +} +#else +static void __maybe_unused +usb_power_config_mx6(void *anatop, int anatop_bits_index) { } +#endif +#if defined(CONFIG_MX7) && !defined(CONFIG_PHY) +static void usb_power_config_mx7(struct usbnc_regs *usbnc) +{ + void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2); + + if (!is_mx7()) + return; + + /* + * Clear the ACAENB to enable usb_otg_id detection, + * otherwise it is the ACA detection enabled. + */ + clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB); +} +#else +static void __maybe_unused +usb_power_config_mx7(void *usbnc) { } #endif + +#if defined(CONFIG_MX7ULP) && !defined(CONFIG_PHY) +static void usb_power_config_mx7ulp(struct usbphy_regs __iomem *usbphy) +{ + if (!is_mx7ulp()) + return; + + writel(ANADIG_USB2_CHRG_DETECT_EN_B | + ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B, + &usbphy->usb1_chrg_detect); + + scg_enable_usb_pll(true); +} +#else +static void __maybe_unused +usb_power_config_mx7ulp(void *usbphy) { } +#endif + +#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) +static const unsigned phy_bases[] = { + USB_PHY0_BASE_ADDR, +#if defined(USB_PHY1_BASE_ADDR) + USB_PHY1_BASE_ADDR, +#endif +}; + +#if !defined(CONFIG_PHY) +static void usb_internal_phy_clock_gate(void __iomem *phy_reg, int on) +{ + phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET; + writel(USBPHY_CTRL_CLKGATE, phy_reg); } /* Return 0 : host node, <>0 : device mode */ @@ -196,6 +224,7 @@ static int usb_phy_enable(struct usb_ehci *ehci, void __iomem *phy_reg) return 0; } +#endif int usb_phy_mode(int port) { @@ -215,19 +244,6 @@ int usb_phy_mode(int port) } #elif defined(CONFIG_MX7) -static void usb_power_config(int index) -{ - struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + - (0x10000 * index) + USBNC_OFFSET); - void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2); - - /* - * Clear the ACAENB to enable usb_otg_id detection, - * otherwise it is the ACA detection enabled. - */ - clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB); -} - int usb_phy_mode(int port) { struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + @@ -325,8 +341,16 @@ int ehci_hcd_init(int index, enum usb_init_type init, enum usb_init_type type; #if defined(CONFIG_MX6) u32 controller_spacing = 0x200; -#elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) + struct anatop_regs __iomem *anatop = + (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; +#elif defined(CONFIG_MX7) + u32 controller_spacing = 0x10000; + struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + + (0x10000 * index) + USBNC_OFFSET); +#elif defined(CONFIG_MX7ULP) u32 controller_spacing = 0x10000; + struct usbphy_regs __iomem *usbphy = + (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR; #endif struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR + (controller_spacing * index)); @@ -353,7 +377,14 @@ int ehci_hcd_init(int index, enum usb_init_type init, return ret; } - usb_power_config(index); +#if defined(CONFIG_MX6) + usb_power_config_mx6(anatop, index); +#elif defined (CONFIG_MX7) + usb_power_config_mx7(usbnc); +#elif defined (CONFIG_MX7ULP) + usb_power_config_mx7ulp(usbphy); +#endif + usb_oc_config(index); #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) @@ -410,10 +441,15 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev) enum usb_init_type type = priv->init_type; struct usb_ehci *ehci = priv->ehci; - usb_power_config(priv->portnr); +#if !defined(CONFIG_PHY) + usb_power_config_mx6(priv->anatop_addr, priv->portnr); + usb_power_config_mx7(priv->misc_addr); + usb_power_config_mx7ulp(priv->phy_addr); +#endif + usb_oc_config(priv->portnr); -#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) +#if !defined(CONFIG_PHY) && (defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)) usb_internal_phy_clock_gate(priv->phy_addr, 1); usb_phy_enable(ehci, priv->phy_addr); #endif @@ -655,10 +691,15 @@ static int ehci_usb_probe(struct udevice *dev) debug("%s: No vbus supply\n", dev->name); #endif - usb_power_config(priv->portnr); +#if !defined(CONFIG_PHY) + usb_power_config_mx6(priv->anatop_addr, priv->portnr); + usb_power_config_mx7(priv->misc_addr); + usb_power_config_mx7ulp(priv->phy_addr); +#endif + usb_oc_config(priv->portnr); -#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) +#if !defined(CONFIG_PHY) && (defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)) usb_internal_phy_clock_gate(priv->phy_addr, 1); usb_phy_enable(ehci, priv->phy_addr); #endif