| Message ID | 20210408102657.201027-9-green.wan@sifive.com |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | Add FU740 chip and HiFive Unmatched board support | expand |
On Thu, Apr 8, 2021 at 6:27 PM Green Wan <green.wan@sifive.com> wrote: > > From: Greentime Hu <greentime.hu@sifive.com> > > Change CPU speed from 1GHz to 1.2Hz > > Signed-off-by: Greentime Hu <greentime.hu@sifive.com> > Tested-by: Green Wan <green.wan@sifive.com> > --- > arch/riscv/dts/fu740-c000-u-boot.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi > index 0115a449f6..e104b47f04 100644 > --- a/arch/riscv/dts/fu740-c000-u-boot.dtsi > +++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi > @@ -9,6 +9,7 @@ > cpus { > assigned-clocks = <&prci PRCI_CLK_COREPLL>; > assigned-clock-rates = <1001000000>; > + assigned-clock-rates = <1200000000>; Two same properties? > u-boot,dm-spl; > cpu0: cpu@0 { > clocks = <&prci PRCI_CLK_COREPLL>; This patch should be squashed into patch [1/8] Regards, Bin
Bin Meng <bmeng.cn@gmail.com>於 2021年4月8日 週四，下午8:10寫道： > On Thu, Apr 8, 2021 at 6:27 PM Green Wan <green.wan@sifive.com> wrote: > > > > From: Greentime Hu <greentime.hu@sifive.com> > > > > Change CPU speed from 1GHz to 1.2Hz > > > > Signed-off-by: Greentime Hu <greentime.hu@sifive.com> > > Tested-by: Green Wan <green.wan@sifive.com> > > --- > > arch/riscv/dts/fu740-c000-u-boot.dtsi | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi > b/arch/riscv/dts/fu740-c000-u-boot.dtsi > > index 0115a449f6..e104b47f04 100644 > > --- a/arch/riscv/dts/fu740-c000-u-boot.dtsi > > +++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi > > @@ -9,6 +9,7 @@ > > cpus { > > assigned-clocks = <&prci PRCI_CLK_COREPLL>; > > assigned-clock-rates = <1001000000>; > > + assigned-clock-rates = <1200000000>; > > Two same properties? It should be only one property. I will fix it. > > > u-boot,dm-spl; > > cpu0: cpu@0 { > > clocks = <&prci PRCI_CLK_COREPLL>; > > This patch should be squashed into patch [1/8] > Ok, Will do it. > Regards, > Bin >
diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi index 0115a449f6..e104b47f04 100644 --- a/arch/riscv/dts/fu740-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi @@ -9,6 +9,7 @@ cpus { assigned-clocks = <&prci PRCI_CLK_COREPLL>; assigned-clock-rates = <1001000000>; + assigned-clock-rates = <1200000000>; u-boot,dm-spl; cpu0: cpu@0 { clocks = <&prci PRCI_CLK_COREPLL>;