| Message ID | 20210315075916.26336-1-elly.siew.chin.lim@intel.com |
|---|---|
| State | Accepted |
| Commit | f86ed75059966e9cf1964b95850058e5a63683e4 |
| Delegated to: | Simon Goldschmidt |
| Headers | show |
| Series | arm: socfpga: Move Stratix10 and Agilex SPL common code | expand |
> -----Original Message----- > From: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com> > Sent: Monday, March 15, 2021 3:59 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut <marex@denx.de>; Tan, Ley Foon > <ley.foon.tan@intel.com>; See, Chin Liang <chin.liang.see@intel.com>; > Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong > <tien.fong.chee@intel.com>; Westergreen, Dalon > <dalon.westergreen@intel.com>; Simon Glass <sjg@chromium.org>; Gan, > Yau Wai <yau.wai.gan@intel.com>; Lim, Elly Siew Chin > <elly.siew.chin.lim@intel.com> > Subject: [PATCH] arm: socfpga: Move Stratix10 and Agilex SPL common code > > Move Stratix10 and Agilex SPL common code to spl_soc64.c. > We are in preparation for new n5x device support. > No functional change in this patch. > > Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 9e63296b38..e4c2da93d5 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -70,10 +70,12 @@ endif ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += firewall.o obj-y += spl_s10.o +obj-y += spl_soc64.o endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += firewall.o obj-y += spl_agilex.o +obj-y += spl_soc64.o endif else obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index 71b17ce3a5..ee5a9dc1e2 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -25,22 +25,6 @@ DECLARE_GLOBAL_DATA_PTR; -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_MMC1; -} - -#ifdef CONFIG_SPL_MMC_SUPPORT -u32 spl_mmc_boot_mode(const u32 boot_device) -{ -#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) - return MMCSD_MODE_FS; -#else - return MMCSD_MODE_RAW; -#endif -} -#endif - void board_init_f(ulong dummy) { int ret; diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index 955a1161e8..c20e87cdbe 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -26,23 +26,6 @@ DECLARE_GLOBAL_DATA_PTR; -u32 spl_boot_device(void) -{ - /* TODO: Get from SDM or handoff */ - return BOOT_DEVICE_MMC1; -} - -#ifdef CONFIG_SPL_MMC_SUPPORT -u32 spl_mmc_boot_mode(const u32 boot_device) -{ -#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) - return MMCSD_MODE_FS; -#else - return MMCSD_MODE_RAW; -#endif -} -#endif - void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c new file mode 100644 index 0000000000..cb98ab39e4 --- /dev/null +++ b/arch/arm/mach-socfpga/spl_soc64.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved + * + */ + +#include <common.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +#if IS_ENABLED(CONFIG_SPL_MMC_SUPPORT) +u32 spl_boot_mode(const u32 boot_device) +{ + if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4)) + return MMCSD_MODE_FS; + else + return MMCSD_MODE_RAW; +} +#endif
Move Stratix10 and Agilex SPL common code to spl_soc64.c. We are in preparation for new n5x device support. No functional change in this patch. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> --- arch/arm/mach-socfpga/Makefile | 2 ++ arch/arm/mach-socfpga/spl_agilex.c | 16 ---------------- arch/arm/mach-socfpga/spl_s10.c | 17 ----------------- arch/arm/mach-socfpga/spl_soc64.c | 25 +++++++++++++++++++++++++ 4 files changed, 27 insertions(+), 33 deletions(-) create mode 100644 arch/arm/mach-socfpga/spl_soc64.c