From patchwork Sun Feb 28 14:12:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1445250 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2021 header.b=UKChxZQj; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DpQNQ4bBPz9sS8 for ; Mon, 1 Mar 2021 01:13:25 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9D6B281F9C; Sun, 28 Feb 2021 15:13:08 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.b="UKChxZQj"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id AD93181454; Sun, 28 Feb 2021 15:13:01 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FORGED_SPF_HELO,FREEMAIL_FROM, RCVD_IN_SORBS_WEB,SPF_HELO_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from libero.it (smtp-17.italiaonline.it [213.209.10.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C39D780505 for ; Sun, 28 Feb 2021 15:12:58 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id GMoXljE45lChfGMoclwAEQ; Sun, 28 Feb 2021 15:12:58 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1614521578; bh=zdUDFhnoPEU01b4unN3IUHVAFPWb5bpEn06dc+Buhq0=; h=From; b=UKChxZQjNQGg2u33aCYAq9kOOisM5o6cC4B1/Bttn+7BVdUQ7OzGf3KS+Anx6WfQ0 EahDSJoTVwEnNJ1cYWjFYECwUys8JU/skNzmYgfyUxNS+hO0ObPeXXUzGeaUw6nciY D8q8cyp0+/21VyPn0JsF07zDkEkJ3ZHTgpmfADjHG5CSuy9sp8mmfUEbafUQw4k2l+ 7s8xYjmowtpCneVwcGiGy7Oo9BRzkqwnVEQKJsG4+VGjNuR2baRCvGJ8OmhtneTIYU AOF7Aedwt1O7CDQxuRJM4+3Ifv/KGYolKdZ3dfp3mOYPCrO6Ro9uSIWyEuB/kFpOCN +Nnxh9dsN0ckg== X-CNFS-Analysis: v=2.4 cv=S6McfKgP c=1 sm=1 tr=0 ts=603ba4ea cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=cm27Pg_UAAAA:8 a=CNNU2WlDxd8r9xRg_hQA:9 a=xmb-EsYY8bH0VWELuYED:22 a=pHzHmUro8NiASowvMSCR:22 a=n87TN5wuljxrRezIQYnT:22 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH v3 01/12] pinctrl: single: fix format of structure documentation Date: Sun, 28 Feb 2021 15:12:30 +0100 Message-Id: <20210228141241.15931-2-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210228141241.15931-1-dariobin@libero.it> References: <20210228141241.15931-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfLbTggMsQtVuGWm4YQf3jX0OsFxOJrzkCN4kmFz3rI9rOMEZtpu0qtDwEAxUjdZ5Q42m849qY1WxGMyn4qKDSt1Na2QTZx+E94jm37270uQMvcwq/LHW JkZ/dJcg5B+lTcWDGFU9AfZHXB5fW0Cp1rAB4hwSDztree7SPVZftvJAxhM1UuNGAh/hEW0sZ2xVPbsf7aop8OV0PQmMTuRuzwBFQ5aozLJtTo1QVf/57O+Z AMvVQkT78LfmtV4Hh/k3a9NvUaCxQFhhKd+QckrLQIZjhsAn1f9CcWmfZhOE+WcJRpzE3zRGQB6sib/cfJ8XF5p4UptR34zpHy7Ab+Wy02IZ46/xDm1b1ooI K9Hn97JO5xytGoxRngfmD0T7XQMYmg== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean U-Boot adopted the kernel-doc annotation style. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- (no changes since v2) Changes in v2: - Added Simon Glass review tag. drivers/pinctrl/pinctrl-single.c | 45 +++++++++++++++++++++++++------- 1 file changed, 36 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 20c3c82aa9..c9a6c272bf 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -10,23 +10,50 @@ #include #include +/** + * struct single_pdata - platform data + * @base: first configuration register + * @offset: index of last configuration register + * @mask: configuration-value mask bits + * @width: configuration register bit width + * @bits_per_mux: true if one register controls more than one pin + */ struct single_pdata { - fdt_addr_t base; /* first configuration register */ - int offset; /* index of last configuration register */ - u32 mask; /* configuration-value mask bits */ - int width; /* configuration register bit width */ + fdt_addr_t base; + int offset; + u32 mask; + int width; bool bits_per_mux; }; +/** + * struct single_fdt_pin_cfg - pin configuration + * + * This structure is used for the pin configuration parameters in case + * the register controls only one pin. + * + * @reg: configuration register offset + * @val: configuration register value + */ struct single_fdt_pin_cfg { - fdt32_t reg; /* configuration register offset */ - fdt32_t val; /* configuration register value */ + fdt32_t reg; + fdt32_t val; }; +/** + * struct single_fdt_bits_cfg - pin configuration + * + * This structure is used for the pin configuration parameters in case + * the register controls more than one pin. + * + * @reg: configuration register offset + * @val: configuration register value + * @mask: configuration register mask + */ struct single_fdt_bits_cfg { - fdt32_t reg; /* configuration register offset */ - fdt32_t val; /* configuration register value */ - fdt32_t mask; /* configuration register mask */ + fdt32_t reg; + fdt32_t val; + fdt32_t mask; }; /**