diff mbox series

[RESEND,v4,7/7] Makefile: socfpga: Add target to generate hex output for combined spl and dtb

Message ID 20210226165733.7591-8-elly.siew.chin.lim@intel.com
State Superseded
Delegated to: Simon Goldschmidt
Headers show
Series Add Vendor Authorized Boot (VAB) support | expand

Commit Message

Siew Chin Lim Feb. 26, 2021, 4:57 p.m. UTC
From: Dalon Westergreen <dalon.westergreen@intel.com>

Add target to Makefile to generate "u-boot-spl-dtb.hex" for Intel
SOCFPGA SOC64 devices (Stratix 10 and Agilex). "u-boot-spl-dtb.hex"
is hex formatted spl with and offset of CONFIG_SPL_TEXT_BASE. It
combines the spl image and dtb. "u-boot-spl-dtb.hex" is needed to
generate the final configuration bitstream for Intel SOCFPGA SOC64
devices.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>

---
v4:
- Replace CONFIG_TARGET_SOCFPGA_STRATIX10/AGILEX with CONFIG_TARGET_SOCFPGA_SOC64.
- Add this patch into 'VAB' series because it is depending on
  CONFIG_TARGET_SOCFPGA_SOC64 patch.
---
 Makefile                               | 11 ++++++-----
 include/configs/socfpga_soc64_common.h |  2 +-
 scripts/Makefile.spl                   |  7 +++++++
 3 files changed, 14 insertions(+), 6 deletions(-)

Comments

Tan, Ley Foon March 1, 2021, 2:02 a.m. UTC | #1
> -----Original Message-----
> From: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> Sent: Saturday, February 27, 2021 12:58 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Tan, Ley Foon
> <ley.foon.tan@intel.com>; See, Chin Liang <chin.liang.see@intel.com>;
> Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@intel.com>; Westergreen, Dalon
> <dalon.westergreen@intel.com>; Simon Glass <sjg@chromium.org>; Gan,
> Yau Wai <yau.wai.gan@intel.com>; Lim, Elly Siew Chin
> <elly.siew.chin.lim@intel.com>
> Subject: [RESEND v4 7/7] Makefile: socfpga: Add target to generate hex
> output for combined spl and dtb
> 
> From: Dalon Westergreen <dalon.westergreen@intel.com>
> 
> Add target to Makefile to generate "u-boot-spl-dtb.hex" for Intel SOCFPGA
> SOC64 devices (Stratix 10 and Agilex). "u-boot-spl-dtb.hex"
> is hex formatted spl with and offset of CONFIG_SPL_TEXT_BASE. It combines
> the spl image and dtb. "u-boot-spl-dtb.hex" is needed to generate the final
> configuration bitstream for Intel SOCFPGA SOC64 devices.
> 
> Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
> 
> ---
> v4:
> - Replace CONFIG_TARGET_SOCFPGA_STRATIX10/AGILEX with
> CONFIG_TARGET_SOCFPGA_SOC64.
> - Add this patch into 'VAB' series because it is depending on
>   CONFIG_TARGET_SOCFPGA_SOC64 patch.
> ---
>  Makefile                               | 11 ++++++-----
>  include/configs/socfpga_soc64_common.h |  2 +-
>  scripts/Makefile.spl                   |  7 +++++++
>  3 files changed, 14 insertions(+), 6 deletions(-)


Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>

Regards
Ley Foon
diff mbox series

Patch

diff --git a/Makefile b/Makefile
index 079881b62a..c788f12bf4 100644
--- a/Makefile
+++ b/Makefile
@@ -1263,11 +1263,6 @@  OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
 		$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
 		$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R .resetvec)
 
-OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex)
-
-spl/u-boot-spl.hex: spl/u-boot-spl FORCE
-	$(call if_changed,objcopy)
-
 binary_size_check: u-boot-nodtb.bin FORCE
 	@file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
 	map_size=$(shell cat u-boot.map | \
@@ -1936,6 +1931,12 @@  spl/u-boot-spl.bin: spl/u-boot-spl
 	@:
 	$(SPL_SIZE_CHECK)
 
+spl/u-boot-spl-dtb.bin: spl/u-boot-spl
+	@:
+
+spl/u-boot-spl-dtb.hex: spl/u-boot-spl
+	@:
+
 spl/u-boot-spl: tools prepare \
 		$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \
 		$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb)
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index 0e54601257..1cfa190047 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -194,7 +194,7 @@  unsigned int cm_get_l4_sys_free_clk_hz(void);
  * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
  *
  */
-#define CONFIG_SPL_TARGET		"spl/u-boot-spl.hex"
+#define CONFIG_SPL_TARGET		"spl/u-boot-spl-dtb.hex"
 #define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZE
 #define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
 #define CONFIG_SPL_BSS_MAX_SIZE		0x100000	/* 1 MB */
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index ea4e045769..1fd63efdfd 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -229,6 +229,8 @@  ifneq ($(CONFIG_TARGET_SOCFPGA_GEN5)$(CONFIG_TARGET_SOCFPGA_ARRIA10),)
 INPUTS-y	+= $(obj)/$(SPL_BIN).sfp
 endif
 
+INPUTS-$(CONFIG_TARGET_SOCFPGA_SOC64) += $(obj)/u-boot-spl-dtb.hex
+
 ifdef CONFIG_ARCH_SUNXI
 INPUTS-y	+= $(obj)/sunxi-spl.bin
 
@@ -389,6 +391,11 @@  $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE
 MKIMAGEFLAGS_sunxi-spl.bin = -T sunxi_egon \
 	-n $(CONFIG_DEFAULT_DEVICE_TREE)
 
+OBJCOPYFLAGS_u-boot-spl-dtb.hex := -I binary -O ihex --change-address=$(CONFIG_SPL_TEXT_BASE)
+
+$(obj)/u-boot-spl-dtb.hex: $(obj)/u-boot-spl-dtb.bin FORCE
+	$(call if_changed,objcopy)
+
 $(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin FORCE
 	$(call if_changed,mkimage)