From patchwork Tue Feb 23 20:46:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 1443635 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DlWPZ3c2Pz9sVX for ; Wed, 24 Feb 2021 07:49:22 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9914F82ABB; Tue, 23 Feb 2021 21:48:18 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 517A182AA3; Tue, 23 Feb 2021 21:47:25 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail.siol.net (mailoutvs27.siol.net [185.57.226.218]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 576F582AB1 for ; Tue, 23 Feb 2021 21:47:16 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jernej.skrabec@siol.net Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id E75FE52454D; Tue, 23 Feb 2021 21:47:15 +0100 (CET) Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta11.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id vP8o9a5YCbu5; Tue, 23 Feb 2021 21:47:15 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id A894C5244B9; Tue, 23 Feb 2021 21:47:15 +0100 (CET) Received: from kista.localdomain (cpe-86-58-17-133.cable.triera.net [86.58.17.133]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id 79E0B524556; Tue, 23 Feb 2021 21:47:13 +0100 (CET) From: Jernej Skrabec To: jagan@amarulasolutions.com, andre.przywara@arm.com, agust@denx.de Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: [PATCH 13/19] video: sunxi: dw-hdmi: move PHY config to appropriate place Date: Tue, 23 Feb 2021 21:46:25 +0100 Message-Id: <20210223204631.1609597-14-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210223204631.1609597-1-jernej.skrabec@siol.net> References: <20210223204631.1609597-1-jernej.skrabec@siol.net> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Currently sunxi_dw_hdmi_enable() configures PHY timing related parameters. However, sunxi_dw_hdmi_phy_cfg() is better suited place for that. Move the code there. This also allows to easier driver expansion when controller uses different PHY than currently supported (like that in H6). Signed-off-by: Jernej Skrabec --- drivers/video/sunxi/sunxi_dw_hdmi.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 483d57293155..4cc175d714ea 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -114,11 +114,13 @@ static void sunxi_dw_hdmi_phy_init(struct dw_hdmi *hdmi) writel(0x42494E47, &phy->unscramble); } -static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, uint clock, int phy_div) +static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, + const struct display_timing *edid, + int phy_div) { struct sunxi_hdmi_phy * const phy = (struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS); - int div = sunxi_dw_hdmi_get_divider(clock); + int div = sunxi_dw_hdmi_get_divider(edid->pixelclock.typ); u32 tmp; /* @@ -187,6 +189,14 @@ static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, uint clock, int phy_div) writel(0x0F81C405, &phy->unk2); break; } + + if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW) + setbits_le32(&phy->pol, 0x200); + + if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW) + setbits_le32(&phy->pol, 0x100); + + setbits_le32(&phy->ctrl, 0xf << 12); } static void sunxi_dw_hdmi_pll_set(uint clk_khz, int *phy_div) @@ -272,7 +282,7 @@ static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, int phy_div; sunxi_dw_hdmi_pll_set(edid->pixelclock.typ / 1000, &phy_div); - sunxi_dw_hdmi_phy_set(hdmi, edid->pixelclock.typ, phy_div); + sunxi_dw_hdmi_phy_set(hdmi, edid, phy_div); return 0; } @@ -304,14 +314,6 @@ static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp, sunxi_dw_hdmi_lcdc_init(priv->mux, edid, panel_bpp); - if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW) - setbits_le32(&phy->pol, 0x200); - - if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW) - setbits_le32(&phy->pol, 0x100); - - setbits_le32(&phy->ctrl, 0xf << 12); - /* * This is last hdmi access before boot, so scramble addresses * again or othwerwise BSP driver won't work. Dummy read is