diff mbox series

[24/57] arm: Remove tricorder board

Message ID 20210221010634.21310-25-trini@konsulko.com
State New
Delegated to: Tom Rini
Headers show
Series Enforce DM_MMC migration and remove platforms | expand

Commit Message

Tom Rini Feb. 21, 2021, 1:06 a.m. UTC
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.

Cc: Thomas Weber <weber@corscience.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
 arch/arm/mach-omap2/omap3/Kconfig             |   5 -
 board/corscience/tricorder/Kconfig            |  12 -
 board/corscience/tricorder/MAINTAINERS        |   7 -
 board/corscience/tricorder/Makefile           |   9 -
 board/corscience/tricorder/led.c              |  79 ----
 board/corscience/tricorder/tricorder-eeprom.c | 225 -----------
 board/corscience/tricorder/tricorder-eeprom.h |  40 --
 board/corscience/tricorder/tricorder.c        | 208 ----------
 board/corscience/tricorder/tricorder.h        | 358 ------------------
 configs/tricorder_defconfig                   |  56 ---
 configs/tricorder_flash_defconfig             |  52 ---
 include/configs/tricorder.h                   | 236 ------------
 12 files changed, 1287 deletions(-)
 delete mode 100644 board/corscience/tricorder/Kconfig
 delete mode 100644 board/corscience/tricorder/MAINTAINERS
 delete mode 100644 board/corscience/tricorder/Makefile
 delete mode 100644 board/corscience/tricorder/led.c
 delete mode 100644 board/corscience/tricorder/tricorder-eeprom.c
 delete mode 100644 board/corscience/tricorder/tricorder-eeprom.h
 delete mode 100644 board/corscience/tricorder/tricorder.c
 delete mode 100644 board/corscience/tricorder/tricorder.h
 delete mode 100644 configs/tricorder_defconfig
 delete mode 100644 configs/tricorder_flash_defconfig
 delete mode 100644 include/configs/tricorder.h
diff mbox series

Patch

diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig
index 0a6eb4cb26d0..16e449cca026 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -97,10 +97,6 @@  config TARGET_OMAP3_PANDORA
 	select OMAP3_GPIO_4
 	select OMAP3_GPIO_6
 
-config TARGET_TRICORDER
-	bool "Tricorder"
-	select OMAP3_GPIO_2
-
 config TARGET_OMAP3_LOGIC
 	bool "OMAP3 Logic"
 	select BOARD_LATE_INIT
@@ -167,7 +163,6 @@  source "board/timll/devkit8000/Kconfig"
 source "board/ti/evm/Kconfig"
 source "board/isee/igep00x0/Kconfig"
 source "board/ti/am3517crane/Kconfig"
-source "board/corscience/tricorder/Kconfig"
 source "board/logicpd/omap3som/Kconfig"
 source "board/nokia/rx51/Kconfig"
 source "board/technexion/tao3530/Kconfig"
diff --git a/board/corscience/tricorder/Kconfig b/board/corscience/tricorder/Kconfig
deleted file mode 100644
index 345ac83d48a8..000000000000
--- a/board/corscience/tricorder/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@ 
-if TARGET_TRICORDER
-
-config SYS_BOARD
-	default "tricorder"
-
-config SYS_VENDOR
-	default "corscience"
-
-config SYS_CONFIG_NAME
-	default "tricorder"
-
-endif
diff --git a/board/corscience/tricorder/MAINTAINERS b/board/corscience/tricorder/MAINTAINERS
deleted file mode 100644
index 8a8171b550c2..000000000000
--- a/board/corscience/tricorder/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@ 
-TRICORDER BOARD
-M:	Thomas Weber <weber@corscience.de>
-S:	Maintained
-F:	board/corscience/tricorder/
-F:	include/configs/tricorder.h
-F:	configs/tricorder_defconfig
-F:	configs/tricorder_flash_defconfig
diff --git a/board/corscience/tricorder/Makefile b/board/corscience/tricorder/Makefile
deleted file mode 100644
index bee39a4f6a3b..000000000000
--- a/board/corscience/tricorder/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@ 
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2012
-# Thomas Weber <weber@corscience.de>
-
-obj-y	:= tricorder.o tricorder-eeprom.o led.o
diff --git a/board/corscience/tricorder/led.c b/board/corscience/tricorder/led.c
deleted file mode 100644
index d876dd7b9f57..000000000000
--- a/board/corscience/tricorder/led.c
+++ /dev/null
@@ -1,79 +0,0 @@ 
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2013 Corscience GmbH & Co.KG
- * Andreas Bießmann <andreas.biessmann@corscience.de>
- */
-#include <common.h>
-#include <status_led.h>
-#include <twl4030.h>
-#include <asm/arch/cpu.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-
-#define TRICORDER_STATUS_LED_YELLOW 42
-#define TRICORDER_STATUS_LED_GREEN  43
-
-void __led_init(led_id_t mask, int state)
-{
-	__led_set(mask, state);
-}
-
-void __led_toggle(led_id_t mask)
-{
-	int toggle_gpio = 0;
-#ifdef CONFIG_LED_STATUS0
-	if (!toggle_gpio && CONFIG_LED_STATUS_BIT & mask)
-		toggle_gpio = TRICORDER_STATUS_LED_GREEN;
-#endif
-#ifdef CONFIG_LED_STATUS1
-	if (!toggle_gpio && CONFIG_LED_STATUS_BIT1 & mask)
-		toggle_gpio = TRICORDER_STATUS_LED_YELLOW;
-#endif
-#ifdef CONFIG_LED_STATUS2
-	if (!toggle_gpio && CONFIG_LED_STATUS_BIT2 & mask) {
-		uint8_t val;
-		twl4030_i2c_read_u8(TWL4030_CHIP_LED, TWL4030_LED_LEDEN,
-				    &val);
-		val ^= (TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDAPWM);
-		twl4030_i2c_write_u8(TWL4030_CHIP_LED, TWL4030_LED_LEDEN,
-				     val);
-	}
-#endif
-	if (toggle_gpio) {
-		int state;
-		gpio_request(toggle_gpio, "");
-		state = gpio_get_value(toggle_gpio);
-		gpio_set_value(toggle_gpio, !state);
-	}
-}
-
-void __led_set(led_id_t mask, int state)
-{
-#ifdef CONFIG_LED_STATUS0
-	if (CONFIG_LED_STATUS_BIT & mask) {
-		gpio_request(TRICORDER_STATUS_LED_GREEN, "");
-		gpio_direction_output(TRICORDER_STATUS_LED_GREEN, 0);
-		gpio_set_value(TRICORDER_STATUS_LED_GREEN, state);
-	}
-#endif
-#ifdef CONFIG_LED_STATUS1
-	if (CONFIG_LED_STATUS_BIT1 & mask) {
-		gpio_request(TRICORDER_STATUS_LED_YELLOW, "");
-		gpio_direction_output(TRICORDER_STATUS_LED_YELLOW, 0);
-		gpio_set_value(TRICORDER_STATUS_LED_YELLOW, state);
-	}
-#endif
-#ifdef CONFIG_LED_STATUS2
-	if (CONFIG_LED_STATUS_BIT2 & mask) {
-		if (CONFIG_LED_STATUS_OFF == state)
-			twl4030_i2c_write_u8(TWL4030_CHIP_LED,
-					     TWL4030_LED_LEDEN, 0);
-		else
-			twl4030_i2c_write_u8(TWL4030_CHIP_LED,
-					     TWL4030_LED_LEDEN,
-					     (TWL4030_LED_LEDEN_LEDAON |
-					      TWL4030_LED_LEDEN_LEDAPWM));
-	}
-#endif
-}
diff --git a/board/corscience/tricorder/tricorder-eeprom.c b/board/corscience/tricorder/tricorder-eeprom.c
deleted file mode 100644
index 192af304d9fb..000000000000
--- a/board/corscience/tricorder/tricorder-eeprom.c
+++ /dev/null
@@ -1,225 +0,0 @@ 
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013
- * Corscience GmbH & Co. KG, <www.corscience.de>
- * Andreas Bießmann <andreas.biessmann@corscience.de>
- */
-#include <common.h>
-#include <command.h>
-#include <eeprom.h>
-#include <i2c.h>
-#include <u-boot/crc.h>
-
-#include "tricorder-eeprom.h"
-
-static inline void warn_wrong_value(const char *msg, unsigned int a,
-		unsigned int b)
-{
-	printf("Expected EEPROM %s %08x, got %08x\n", msg, a, b);
-}
-
-static int handle_eeprom_v0(struct tricorder_eeprom *eeprom)
-{
-	struct tricorder_eeprom_v0 {
-		uint32_t magic;
-		uint16_t length;
-		uint16_t version;
-		char board_name[TRICORDER_BOARD_NAME_LENGTH];
-		char board_version[TRICORDER_BOARD_VERSION_LENGTH];
-		char board_serial[TRICORDER_BOARD_SERIAL_LENGTH];
-		uint32_t crc32;
-	} __packed eepromv0;
-	uint32_t crc;
-
-	printf("Old EEPROM (v0), consider rewrite!\n");
-
-	if (be16_to_cpu(eeprom->length) != sizeof(eepromv0)) {
-		warn_wrong_value("length", sizeof(eepromv0),
-				 be16_to_cpu(eeprom->length));
-		return 1;
-	}
-
-	memcpy(&eepromv0, eeprom, sizeof(eepromv0));
-
-	crc = crc32(0L, (unsigned char *)&eepromv0,
-		    sizeof(eepromv0) - sizeof(eepromv0.crc32));
-	if (be32_to_cpu(eepromv0.crc32) != crc) {
-		warn_wrong_value("CRC", be32_to_cpu(eepromv0.crc32),
-				 crc);
-		return 1;
-	}
-
-	/* Ok the content is correct, do the conversion */
-	memset(eeprom->interface_version, 0x0,
-	       TRICORDER_INTERFACE_VERSION_LENGTH);
-	crc = crc32(0L, (unsigned char *)eeprom, TRICORDER_EEPROM_CRC_SIZE);
-	eeprom->crc32 = cpu_to_be32(crc);
-
-	return 0;
-}
-
-static int handle_eeprom_v1(struct tricorder_eeprom *eeprom)
-{
-	uint32_t crc;
-
-	if (be16_to_cpu(eeprom->length) != TRICORDER_EEPROM_SIZE) {
-		warn_wrong_value("length", TRICORDER_EEPROM_SIZE,
-				 be16_to_cpu(eeprom->length));
-		return 1;
-	}
-
-	crc = crc32(0L, (unsigned char *)eeprom, TRICORDER_EEPROM_CRC_SIZE);
-	if (be32_to_cpu(eeprom->crc32) != crc) {
-		warn_wrong_value("CRC", be32_to_cpu(eeprom->crc32), crc);
-		return 1;
-	}
-
-	return 0;
-}
-
-int tricorder_get_eeprom(int addr, struct tricorder_eeprom *eeprom)
-{
-	unsigned int bus = i2c_get_bus_num();
-	i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
-
-	memset(eeprom, 0, TRICORDER_EEPROM_SIZE);
-
-	i2c_read(addr, 0, 2, (unsigned char *)eeprom, TRICORDER_EEPROM_SIZE);
-	i2c_set_bus_num(bus);
-
-	if (be32_to_cpu(eeprom->magic) != TRICORDER_EEPROM_MAGIC) {
-		warn_wrong_value("magic", TRICORDER_EEPROM_MAGIC,
-				 be32_to_cpu(eeprom->magic));
-		return 1;
-	}
-
-	switch (be16_to_cpu(eeprom->version)) {
-	case 0:
-		return handle_eeprom_v0(eeprom);
-	case 1:
-		return handle_eeprom_v1(eeprom);
-	default:
-		warn_wrong_value("version", TRICORDER_EEPROM_VERSION,
-				 be16_to_cpu(eeprom->version));
-		return 1;
-	}
-}
-
-#if !defined(CONFIG_SPL)
-int tricorder_eeprom_read(unsigned devaddr)
-{
-	struct tricorder_eeprom eeprom;
-	int ret = tricorder_get_eeprom(devaddr, &eeprom);
-
-	if (ret)
-		return ret;
-
-	printf("Board type:               %.*s\n",
-	       sizeof(eeprom.board_name), eeprom.board_name);
-	printf("Board version:            %.*s\n",
-	       sizeof(eeprom.board_version), eeprom.board_version);
-	printf("Board serial:             %.*s\n",
-	       sizeof(eeprom.board_serial), eeprom.board_serial);
-	printf("Board interface version:  %.*s\n",
-	       sizeof(eeprom.interface_version),
-	       eeprom.interface_version);
-
-	return ret;
-}
-
-int tricorder_eeprom_write(unsigned devaddr, const char *name,
-		const char *version, const char *serial, const char *interface)
-{
-	struct tricorder_eeprom eeprom, eeprom_verify;
-	size_t length;
-	uint32_t crc;
-	int ret;
-	unsigned char *p;
-	int i;
-
-	memset(eeprom, 0, TRICORDER_EEPROM_SIZE);
-	memset(eeprom_verify, 0, TRICORDER_EEPROM_SIZE);
-
-	eeprom.magic = cpu_to_be32(TRICORDER_EEPROM_MAGIC);
-	eeprom.length = cpu_to_be16(TRICORDER_EEPROM_SIZE);
-	eeprom.version = cpu_to_be16(TRICORDER_EEPROM_VERSION);
-
-	length = min(sizeof(eeprom.board_name), strlen(name));
-	strncpy(eeprom.board_name, name, length);
-
-	length = min(sizeof(eeprom.board_version), strlen(version));
-	strncpy(eeprom.board_version, version, length);
-
-	length = min(sizeof(eeprom.board_serial), strlen(serial));
-	strncpy(eeprom.board_serial, serial, length);
-
-	if (interface) {
-		length = min(sizeof(eeprom.interface_version),
-				strlen(interface));
-		strncpy(eeprom.interface_version, interface, length);
-	}
-
-	crc = crc32(0L, (unsigned char *)&eeprom, TRICORDER_EEPROM_CRC_SIZE);
-	eeprom.crc32 = cpu_to_be32(crc);
-
-#if defined(DEBUG)
-	puts("Tricorder EEPROM content:\n");
-	print_buffer(0, &eeprom, 1, sizeof(eeprom), 16);
-#endif
-
-	eeprom_init(CONFIG_SYS_EEPROM_BUS_NUM);
-
-	ret = eeprom_write(devaddr, 0, (unsigned char *)&eeprom,
-			TRICORDER_EEPROM_SIZE);
-	if (ret)
-		printf("Tricorder: Could not write EEPROM content!\n");
-
-	ret = eeprom_read(devaddr, 0, (unsigned char *)&eeprom_verify,
-			TRICORDER_EEPROM_SIZE);
-	if (ret)
-		printf("Tricorder: Could not read EEPROM content!\n");
-
-	if (memcmp(&eeprom, &eeprom_verify, sizeof(eeprom)) != 0) {
-		printf("Tricorder: Could not verify EEPROM content!\n");
-		ret = 1;
-	}
-
-	return ret;
-}
-
-int do_tricorder_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *argv[])
-{
-	if (argc == 3) {
-		ulong dev_addr = simple_strtoul(argv[2], NULL, 16);
-
-		if (strcmp(argv[1], "read") == 0)
-			return tricorder_eeprom_read(dev_addr);
-	} else if (argc == 6 || argc == 7) {
-		ulong dev_addr = simple_strtoul(argv[2], NULL, 16);
-		char *name = argv[3];
-		char *version = argv[4];
-		char *serial = argv[5];
-		char *interface = NULL;
-
-		if (argc == 7)
-			interface = argv[6];
-
-		if (strcmp(argv[1], "write") == 0)
-			return tricorder_eeprom_write(dev_addr, name, version,
-						      serial, interface);
-	}
-
-	return CMD_RET_USAGE;
-}
-
-U_BOOT_CMD(
-	tricordereeprom,	7,	1,	do_tricorder_eeprom,
-	"Tricorder EEPROM",
-	"read  devaddr\n"
-	"       - read Tricorder EEPROM at devaddr and print content\n"
-	"tricordereeprom write devaddr name version serial [interface]\n"
-	"       - write Tricorder EEPROM at devaddr with 'name', 'version'"
-	"and 'serial'\n"
-	"         optional add an HW interface parameter"
-);
-#endif /* CONFIG_SPL */
diff --git a/board/corscience/tricorder/tricorder-eeprom.h b/board/corscience/tricorder/tricorder-eeprom.h
deleted file mode 100644
index 7107b02a2c10..000000000000
--- a/board/corscience/tricorder/tricorder-eeprom.h
+++ /dev/null
@@ -1,40 +0,0 @@ 
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013
- * Corscience GmbH & Co. KG, <www.corscience.de>
- * Andreas Bießmann <andreas.biessmann@corscience.de>
- */
-#ifndef TRICORDER_EEPROM_H_
-#define TRICORDER_EEPROM_H_
-
-#include <linux/compiler.h>
-
-#define TRICORDER_EEPROM_MAGIC 0xc2a94f52
-#define TRICORDER_EEPROM_VERSION 1
-
-#define TRICORDER_BOARD_NAME_LENGTH		12
-#define TRICORDER_BOARD_VERSION_LENGTH		4
-#define TRICORDER_BOARD_SERIAL_LENGTH		12
-#define TRICORDER_INTERFACE_VERSION_LENGTH	4
-
-struct tricorder_eeprom {
-	uint32_t magic;
-	uint16_t length;
-	uint16_t version;
-	char board_name[TRICORDER_BOARD_NAME_LENGTH];
-	char board_version[TRICORDER_BOARD_VERSION_LENGTH];
-	char board_serial[TRICORDER_BOARD_SERIAL_LENGTH];
-	char interface_version[TRICORDER_INTERFACE_VERSION_LENGTH];
-	uint32_t crc32;
-} __packed;
-
-#define TRICORDER_EEPROM_SIZE		sizeof(struct tricorder_eeprom)
-#define TRICORDER_EEPROM_CRC_SIZE	(TRICORDER_EEPROM_SIZE - \
-					 sizeof(uint32_t))
-
-/**
- * @brief read eeprom information from a specific eeprom address
- */
-int tricorder_get_eeprom(int addr, struct tricorder_eeprom *eeprom);
-
-#endif /* TRICORDER_EEPROM_H_ */
diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c
deleted file mode 100644
index 3f4a40fd6593..000000000000
--- a/board/corscience/tricorder/tricorder.c
+++ /dev/null
@@ -1,208 +0,0 @@ 
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2012
- * Corscience GmbH & Co. KG, <www.corscience.de>
- * Thomas Weber <weber@corscience.de>
- * Sunil Kumar <sunilsaini05@gmail.com>
- * Shashi Ranjan <shashiranjanmca05@gmail.com>
- *
- * Derived from Devkit8000 code by
- * Frederik Kriewitz <frederik@kriewitz.eu>
- */
-#include <common.h>
-#include <init.h>
-#include <malloc.h>
-#include <twl4030.h>
-#include <status_led.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mem.h>
-#include "tricorder.h"
-#include "tricorder-eeprom.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
-	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
-	/* boot param addr */
-	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-	return 0;
-}
-
-/**
- * get_eeprom - read the eeprom
- *
- * @eeprom - pointer to a eeprom struct to fill
- *
- * This function will panic() on wrong EEPROM content
- */
-static void get_eeprom(struct tricorder_eeprom *eeprom)
-{
-	int ret;
-
-	if (!eeprom)
-		panic("No eeprom given!\n");
-
-	ret = gpio_request(7, "BMS");
-	if (ret)
-		panic("gpio: requesting BMS pin failed\n");
-
-	ret = gpio_direction_input(7);
-	if (ret)
-		panic("gpio: set BMS as input failed\n");
-
-	ret = gpio_get_value(7);
-	if (ret < 0)
-		panic("gpio: get BMS pin state failed\n");
-
-	gpio_free(7);
-
-	if (ret == 0) {
-		/* BMS is _not_ set, do the EEPROM check */
-		ret = tricorder_get_eeprom(0x51, eeprom);
-		if (!ret) {
-			if (strncmp(eeprom->board_name, "CS10411", 7) != 0)
-				panic("Wrong board name '%.*s'\n",
-				      sizeof(eeprom->board_name),
-						eeprom->board_name);
-			if (eeprom->board_version[0] < 'D')
-				panic("Wrong board version '%.*s'\n",
-				      sizeof(eeprom->board_version),
-						eeprom->board_version);
-		} else {
-			panic("Could not get board revision\n");
-		}
-	} else {
-		memset(eeprom, 0, TRICORDER_EEPROM_SIZE);
-	}
-}
-
-/**
- * print_hwversion - print out a HW version string
- *
- * @eeprom - pointer to the eeprom
- */
-static void print_hwversion(struct tricorder_eeprom *eeprom)
-{
-	size_t len;
-	if (!eeprom)
-		panic("No eeprom given!");
-
-	printf("Board %.*s:%.*s serial %.*s",
-	       sizeof(eeprom->board_name), eeprom->board_name,
-	       sizeof(eeprom->board_version), eeprom->board_version,
-	       sizeof(eeprom->board_serial), eeprom->board_serial);
-
-	len = strnlen(eeprom->interface_version,
-		      sizeof(eeprom->interface_version));
-	if (len > 0)
-		printf(" HW interface version %.*s",
-		       sizeof(eeprom->interface_version),
-		       eeprom->interface_version);
-	puts("\n");
-}
-
-/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-int misc_init_r(void)
-{
-	struct tricorder_eeprom eeprom;
-	get_eeprom(&eeprom);
-	print_hwversion(&eeprom);
-
-	twl4030_power_init();
-	status_led_set(0, CONFIG_LED_STATUS_ON);
-	status_led_set(1, CONFIG_LED_STATUS_ON);
-	status_led_set(2, CONFIG_LED_STATUS_ON);
-
-	omap_die_id_display();
-
-	return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- *		hardware. Many pins need to be moved from protect to primary
- *		mode.
- */
-void set_muxconf_regs(void)
-{
-	MUX_TRICORDER();
-}
-
-#if defined(CONFIG_MMC)
-int board_mmc_init(struct bd_info *bis)
-{
-	return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#if defined(CONFIG_MMC)
-void board_mmc_power_init(void)
-{
-	twl4030_power_mmc_init(0);
-}
-#endif
-
-/*
- * Routine: get_board_mem_timings
- * Description: If we use SPL then there is no x-loader nor config header
- * so we have to setup the DDR timings ourself on the first bank.  This
- * provides the timing values back to the function that configures
- * the memory.  We have either one or two banks of 128MB DDR.
- */
-void get_board_mem_timings(struct board_sdrc_timings *timings)
-{
-	struct tricorder_eeprom eeprom;
-	get_eeprom(&eeprom);
-
-	/* General SDRC config */
-	if (eeprom.board_version[0] > 'D') {
-		/* use optimized timings for our SDRAM device */
-		timings->mcfg = MCFG((256 << 20), 14);
-#define MT46H64M32_TDAL  6	/* Twr/Tck + Trp/tck		*/
-				/* 15/6 + 18/6 = 5.5 -> 6	*/
-#define MT46H64M32_TDPL  3	/* 15/6 = 2.5 -> 3 (Twr)	*/
-#define MT46H64M32_TRRD  2	/* 12/6 = 2			*/
-#define MT46H64M32_TRCD  3	/* 18/6 = 3			*/
-#define MT46H64M32_TRP   3	/* 18/6 = 3			*/
-#define MT46H64M32_TRAS  7	/* 42/6 = 7			*/
-#define MT46H64M32_TRC  10	/* 60/6 = 10			*/
-#define MT46H64M32_TRFC 12	/* 72/6 = 12			*/
-		timings->ctrla = ACTIM_CTRLA(MT46H64M32_TRFC, MT46H64M32_TRC,
-					     MT46H64M32_TRAS, MT46H64M32_TRP,
-					     MT46H64M32_TRCD, MT46H64M32_TRRD,
-					     MT46H64M32_TDPL,
-					     MT46H64M32_TDAL);
-
-#define MT46H64M32_TWTR 1
-#define MT46H64M32_TCKE 1
-#define MT46H64M32_XSR 19	/* 112.5/6 = 18.75 => ~19	*/
-#define MT46H64M32_TXP 1
-		timings->ctrlb = ACTIM_CTRLB(MT46H64M32_TWTR, MT46H64M32_TCKE,
-					     MT46H64M32_TXP, MT46H64M32_XSR);
-
-		timings->mr = MICRON_V_MR_165;
-		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
-	} else {
-		/* use conservative beagleboard timings as default */
-		timings->mcfg = MICRON_V_MCFG_165(128 << 20);
-		timings->ctrla = MICRON_V_ACTIMA_165;
-		timings->ctrlb = MICRON_V_ACTIMB_165;
-		timings->mr = MICRON_V_MR_165;
-		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
-	}
-}
diff --git a/board/corscience/tricorder/tricorder.h b/board/corscience/tricorder/tricorder.h
deleted file mode 100644
index f083a5e9a22d..000000000000
--- a/board/corscience/tricorder/tricorder.h
+++ /dev/null
@@ -1,358 +0,0 @@ 
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008
- * Dirk Behme <dirk.behme@gmail.com>
- *
- * (C) Copyright 2012
- * Corscience GmbH & Co. KG, <www.corscience.de>
- * Thomas Weber <weber@corscience.de>
- */
-#ifndef _TRICORDER_H_
-#define _TRICORDER_H_
-
-const omap3_sysinfo sysinfo = {
-	DDR_STACKED,
-	"OMAP3 Tricorder",
-	"NAND",
-};
-
-/*
- * IEN  - Input Enable
- * IDIS - Input Disable
- * PTD  - Pull type Down
- * PTU  - Pull type Up
- * DIS  - Pull type selection is inactive
- * EN   - Pull type selection is active
- * M0   - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_TRICORDER() \
-	/* SDRC */\
-	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
-	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
-	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
-	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
-	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
-	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
-	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
-	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
-	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
-	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
-	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
-	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
-	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
-	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
-	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
-	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
-	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
-	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
-	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
-	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
-	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
-	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
-	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
-	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
-	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
-	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
-	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
-	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
-	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
-	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
-	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
-	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
-	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
-	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
-	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
-	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
-	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
-	/* GPMC */\
-	MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
-	MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
-	MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
-	MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
-	MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
-	MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
-	MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
-	MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
-	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M4)) /*GPIO 42*/\
-	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M4)) /*GPIO 43*/\
-	MUX_VAL(CP(GPMC_D0),		(IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
-	MUX_VAL(CP(GPMC_D1),		(IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
-	MUX_VAL(CP(GPMC_D2),		(IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
-	MUX_VAL(CP(GPMC_D3),		(IEN  | PTD | DIS | M0)) /*GPMC_D3*/\
-	MUX_VAL(CP(GPMC_D4),		(IEN  | PTD | DIS | M0)) /*GPMC_D4*/\
-	MUX_VAL(CP(GPMC_D5),		(IEN  | PTD | DIS | M0)) /*GPMC_D5*/\
-	MUX_VAL(CP(GPMC_D6),		(IEN  | PTD | DIS | M0)) /*GPMC_D6*/\
-	MUX_VAL(CP(GPMC_D7),		(IEN  | PTD | DIS | M0)) /*GPMC_D7*/\
-	MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0)) /*GPMC_D8*/\
-	MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0)) /*GPMC_D9*/\
-	MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0)) /*GPMC_D10*/\
-	MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0)) /*GPMC_D11*/\
-	MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0)) /*GPMC_D12*/\
-	MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0)) /*GPMC_D13*/\
-	MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0)) /*GPMC_D14*/\
-	MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0)) /*GPMC_D15*/\
-	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0 NAND*/\
-	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
-	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
-	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS3*/\
-	MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS4*/\
-	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS5*/\
-	MUX_VAL(CP(GPMC_NCS6),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS6*/\
-	MUX_VAL(CP(GPMC_NCS7),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS7*/\
-	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | DIS | M0)) /*GPMC_nBE1*/\
-	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT2*/\
-	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/\
-	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
-	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
-	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
-	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
-	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
-	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
-	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
-	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
-	/* DSS */\
-	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
-	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
-	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
-	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
-	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
-	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
-	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
-	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
-	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
-	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
-	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
-	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
-	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
-	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
-	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
-	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
-	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
-	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
-	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
-	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
-	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
-	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
-	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
-	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
-	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
-	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
-	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
-	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
-	/* CAMERA */\
-	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) /*CAM_HS */\
-	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) /*CAM_VS */\
-	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
-	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
-	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
-	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) /*CAM_D0*/\
-	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) /*CAM_D1*/\
-	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) /*CAM_D2*/\
-	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) /*CAM_D3*/\
-	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) /*CAM_D4*/\
-	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) /*CAM_D5*/\
-	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) /*CAM_D6*/\
-	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) /*CAM_D7*/\
-	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) /*CAM_D8*/\
-	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) /*CAM_D9*/\
-	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) /*CAM_D10*/\
-	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) /*CAM_D11*/\
-	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
-	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
-	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
-	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
-	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
-	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
-	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
-	/* Audio Interface */\
-	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
-	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
-	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
-	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
-	/* MMC Slot */\
-	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
-	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
-	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
-	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
-	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
-	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
-	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
-	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
-	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
-	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
-	/* Expansion Header */\
-	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_130*/\
-	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M4)) /*GPIO_131*/\
-	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M4)) /*GPIO_132*/\
-	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M4)) /*GPIO_133*/\
-	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M4)) /*GPIO_134*/\
-	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M4)) /*GPIO_135*/\
-	MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M4)) /*GPIO_136*/\
-	MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_137*/\
-	MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | EN  | M4)) /*GPIO_138*/\
-	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139*/\
-	MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_140*/\
-	MUX_VAL(CP(MCBSP3_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_141*/\
-	MUX_VAL(CP(MCBSP3_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_142*/\
-	MUX_VAL(CP(MCBSP3_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_143*/\
-	MUX_VAL(CP(UART2_CTS),		(IDIS | PTD | DIS | M4)) /*GPIO_144*/\
-	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_145*/\
-	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M4)) /*GPIO_146*/\
-	MUX_VAL(CP(UART2_RX),		(IDIS | PTD | DIS | M4)) /*GPIO_147*/\
-	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*GPIO_148*/\
-	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
-	MUX_VAL(CP(UART1_CTS),		(IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
-	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*GPIO_151*/\
-	MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | DIS | M1)) /*GPIO_152*/\
-	MUX_VAL(CP(MCBSP4_DR),		(IEN  | PTD | DIS | M1)) /*GPIO_153*/\
-	MUX_VAL(CP(MCBSP4_DX),		(IEN  | PTD | DIS | M1)) /*GPIO_154*/\
-	MUX_VAL(CP(MCBSP4_FSX),		(IEN  | PTD | DIS | M1)) /*GPIO_155*/\
-	MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M4)) /*GPIO_156*/\
-	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M4)) /*GPIO_157*/\
-	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_158*/\
-	MUX_VAL(CP(MCBSP1_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_159*/\
-	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*GPIO_160*/\
-	MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_161*/\
-	MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_162*/\
-	/* Serial Interface */\
-	MUX_VAL(CP(UART3_CTS_RCTX),	(IDIS | PTD | EN  | M4)) /*GPIO_163 - LED2*/\
-	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTU | EN  | M4)) /*GPIO_164 - LED3*/\
-	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
-	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
-	/* Host USB0 */\
-	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
-	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
-	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
-	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
-	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
-	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
-	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
-	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
-	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
-	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
-	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
-	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
-	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
-	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
-	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) /*I2C2_SCL*/\
-	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) /*I2C2_SDA*/\
-	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
-	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
-	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
-	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
-	MUX_VAL(CP(HDQ_SIO),		(IEN  | PTU | EN  | M0)) /*HDQ_SIO*/\
-	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M4)) /*GPIO_171*/\
-	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M4)) /*GPIO_172*/\
-	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) /*MCSPI1_SOMI*/\
-	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | DIS | M0)) /*MCSPI1_CS0*/\
-	MUX_VAL(CP(MCSPI1_CS1),		(IDIS | PTD | DIS | M0)) /*MCSPI1_CS1*/\
-	MUX_VAL(CP(MCSPI1_CS2),		(IDIS | PTD | DIS | M4)) /*GPIO_176*/\
-	/* USB EHCI (port 2) */\
-	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | EN  | M0)) /*HSUSB2_DATA2*/\
-	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB2_DATA7*/\
-	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0)) /*HSUSB2_DATA4*/\
-	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) /*HSUSB2_DATA5*/\
-	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M0)) /*HSUSB2_DATA6*/\
-	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M0)) /*HSUSB2_DATA3*/\
-	/*Control and debug */\
-	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
-	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
-	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
-	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
-	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3*/\
-	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4*/\
-	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
-	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
-	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7 - BOOTMODE*/\
-	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
-	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
-	MUX_VAL(CP(SYS_CLKOUT1),	(IDIS | PTD | EN  | M0)) /*SYS_CLKOUT1*/\
-	MUX_VAL(CP(SYS_CLKOUT2),	(IDIS | PTU | EN  | M4)) /*GPIO_186 - LED1*/\
-	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTD | DIS | M4)) /*GPIO_12*/\
-	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTD | EN  | M4)) /*GPIO_13*/\
-	MUX_VAL(CP(ETK_D0_ES2),		(IDIS | PTU | EN  | M1)) /*SPI3_SIMO*/\
-	MUX_VAL(CP(ETK_D1_ES2),		(IDIS | PTU | EN  | M1)) /*SPI3_SOMI*/\
-	MUX_VAL(CP(ETK_D2_ES2),		(IDIS | PTU | EN  | M1)) /*SPI3_CS0*/\
-	MUX_VAL(CP(ETK_D3_ES2),		(IDIS | PTU | EN  | M1)) /*SPI3_CLK*/\
-	MUX_VAL(CP(ETK_D4_ES2),		(IDIS | PTU | EN  | M4)) /*GPIO_18*/\
-	MUX_VAL(CP(ETK_D5_ES2),		(IDIS | PTU | EN  | M4)) /*GPIO_19*/\
-	MUX_VAL(CP(ETK_D6_ES2),		(IDIS | PTU | EN  | M4)) /*GPIO_20*/\
-	MUX_VAL(CP(ETK_D7_ES2),		(IDIS | PTU | EN  | M1)) /*SPI3_CS1*/\
-	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTU | DIS | M4)) /*MSECURE*/\
-	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTU | EN  | M4)) /*GPIO_23*/\
-	/*HSUSB2 */\
-	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTU | EN  | M4)) /*GPIO_24*/\
-	MUX_VAL(CP(ETK_D11_ES2),	(IEN  | PTU | EN  | M4)) /*GPIO_25*/\
-	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTU | EN  | M4)) /*GPIO_26*/\
-	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTU | EN  | M4)) /*GPIO_27*/\
-	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTU | EN  | M4)) /*GPIO_28*/\
-	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTU | EN  | M4)) /*GPIO_29*/\
-	/* */\
-	MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD1*/\
-	MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD2*/\
-	MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD3*/\
-	MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD4*/\
-	MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD5*/\
-	MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD6*/\
-	MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD7*/\
-	MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD8*/\
-	MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD9*/\
-	MUX_VAL(CP(D2D_MCAD10),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD10*/\
-	MUX_VAL(CP(D2D_MCAD11),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD11*/\
-	MUX_VAL(CP(D2D_MCAD12),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD12*/\
-	MUX_VAL(CP(D2D_MCAD13),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD13*/\
-	MUX_VAL(CP(D2D_MCAD14),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD14*/\
-	MUX_VAL(CP(D2D_MCAD15),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD15*/\
-	MUX_VAL(CP(D2D_MCAD16),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD16*/\
-	MUX_VAL(CP(D2D_MCAD17),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD17*/\
-	MUX_VAL(CP(D2D_MCAD18),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD18*/\
-	MUX_VAL(CP(D2D_MCAD19),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD19*/\
-	MUX_VAL(CP(D2D_MCAD20),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD20*/\
-	MUX_VAL(CP(D2D_MCAD21),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD21*/\
-	MUX_VAL(CP(D2D_MCAD22),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD22*/\
-	MUX_VAL(CP(D2D_MCAD23),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD23*/\
-	MUX_VAL(CP(D2D_MCAD24),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD24*/\
-	MUX_VAL(CP(D2D_MCAD25),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD25*/\
-	MUX_VAL(CP(D2D_MCAD26),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD26*/\
-	MUX_VAL(CP(D2D_MCAD27),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD27*/\
-	MUX_VAL(CP(D2D_MCAD28),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD28*/\
-	MUX_VAL(CP(D2D_MCAD29),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD29*/\
-	MUX_VAL(CP(D2D_MCAD30),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD30*/\
-	MUX_VAL(CP(D2D_MCAD31),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD31*/\
-	MUX_VAL(CP(D2D_MCAD32),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD32*/\
-	MUX_VAL(CP(D2D_MCAD33),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD33*/\
-	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD34*/\
-	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD35*/\
-	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD36*/\
-	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) /*D2D_clk26mi*/\
-	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) /*D2D_nrespwron*/\
-	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) /*D2D_nreswarm */\
-	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) /*D2D_arm9nirq */\
-	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) /*D2D_uma2p6fiq*/\
-	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) /*D2D_spint*/\
-	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) /*D2D_frint*/\
-	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) /*D2D_dmareq0*/\
-	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) /*D2D_dmareq1*/\
-	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) /*D2D_dmareq2*/\
-	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) /*D2D_dmareq3*/\
-	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /*D2D_n3gtrst*/\
-	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) /*D2D_n3gtdi*/\
-	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) /*D2D_n3gtdo*/\
-	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) /*D2D_n3gtms*/\
-	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) /*D2D_n3gtck*/\
-	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /*D2D_n3grtck*/\
-	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) /*D2D_mstdby*/\
-	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /*D2D_swakeup*/\
-	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /*D2D_idlereq*/\
-	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /*D2D_idleack*/\
-	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) /*D2D_mwrite*/\
-	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) /*D2D_swrite*/\
-	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /*D2D_mread*/\
-	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /*D2D_sread*/\
-	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*D2D_mbusflag*/\
-	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*D2D_sbusflag*/\
-	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
-	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
-
-#endif
diff --git a/configs/tricorder_defconfig b/configs/tricorder_defconfig
deleted file mode 100644
index 6e511a1b13b6..000000000000
--- a/configs/tricorder_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@ 
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_TEXT_BASE=0x80100000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x120000
-CONFIG_SPL_TEXT_BASE=0x40200000
-CONFIG_TARGET_TRICORDER=y
-CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x2A0000
-CONFIG_BOOTDELAY=0
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SPL_NAND_DRIVERS=y
-CONFIG_SPL_NAND_ECC=y
-CONFIG_SPL_NAND_SIMPLE=y
-CONFIG_SPL_NAND_BASE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="OMAP3 Tricorder # "
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_EEPROM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_LOCK_UNLOCK=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(SPL),1m(u-boot),384k(u-boot-env1),1152k(mtdoops),384k(u-boot-env2),5m(kernel),2m(fdt),-(ubi)"
-CONFIG_CMD_UBI=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
-CONFIG_LED_STATUS=y
-CONFIG_LED_STATUS0=y
-CONFIG_LED_STATUS_BIT=1
-CONFIG_LED_STATUS_STATE=2
-CONFIG_LED_STATUS1=y
-CONFIG_LED_STATUS_BIT1=2
-CONFIG_LED_STATUS_STATE1=2
-CONFIG_LED_STATUS2=y
-CONFIG_LED_STATUS_BIT2=4
-CONFIG_LED_STATUS_STATE2=2
-CONFIG_LED_STATUS_CMD=y
-CONFIG_TWL4030_LED=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_CONS_INDEX=3
-CONFIG_SYS_NS16550=y
-CONFIG_BCH=y
-CONFIG_PANIC_HANG=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/tricorder_flash_defconfig b/configs/tricorder_flash_defconfig
deleted file mode 100644
index 0ade2d35ca11..000000000000
--- a/configs/tricorder_flash_defconfig
+++ /dev/null
@@ -1,52 +0,0 @@ 
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_TEXT_BASE=0x80100000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_ENV_SIZE=0x4000
-CONFIG_SPL_TEXT_BASE=0x40200000
-CONFIG_TARGET_TRICORDER=y
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="FLASHCARD"
-CONFIG_BOOTDELAY=0
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SPL_NAND_DRIVERS=y
-CONFIG_SPL_NAND_ECC=y
-CONFIG_SPL_NAND_SIMPLE=y
-CONFIG_SPL_NAND_BASE=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_EEPROM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_LOCK_UNLOCK=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(SPL),1m(u-boot),384k(u-boot-env1),1152k(mtdoops),384k(u-boot-env2),5m(kernel),2m(fdt),-(ubi)"
-CONFIG_CMD_UBI=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
-CONFIG_LED_STATUS=y
-CONFIG_LED_STATUS0=y
-CONFIG_LED_STATUS_BIT=1
-CONFIG_LED_STATUS_STATE=2
-CONFIG_LED_STATUS1=y
-CONFIG_LED_STATUS_BIT1=2
-CONFIG_LED_STATUS_STATE1=2
-CONFIG_LED_STATUS2=y
-CONFIG_LED_STATUS_BIT2=4
-CONFIG_LED_STATUS_STATE2=2
-CONFIG_LED_STATUS_CMD=y
-CONFIG_TWL4030_LED=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_CONS_INDEX=3
-CONFIG_SYS_NS16550=y
-CONFIG_BCH=y
-CONFIG_PANIC_HANG=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
deleted file mode 100644
index 55f25857eb3d..000000000000
--- a/include/configs/tricorder.h
+++ /dev/null
@@ -1,236 +0,0 @@ 
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2006-2008
- * Texas Instruments.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <x0khasim@ti.com>
- *
- * (C) Copyright 2012
- * Corscience GmbH & Co. KG
- * Thomas Weber <weber@corscience.de>
- *
- * Configuration settings for the Tricorder board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MACH_TYPE		MACH_TYPE_TRICORDER
-/*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
- * other needs.
- */
-
-#include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap.h>
-
-/* Clock Defines */
-#define V_OSCK				26000000 /* Clock output from T2 */
-#define V_SCLK				(V_OSCK >> 1)
-
-#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(1024*1024)
-
-/* Hardware drivers */
-
-/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		48000000 /* 48MHz (APLL96/2) */
-
-/* select serial console configuration */
-#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
-#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
-					115200}
-
-/* I2C */
-#define CONFIG_SYS_I2C
- 
-
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
-#define CONFIG_SYS_EEPROM_BUS_NUM	1
-
-/* TWL4030 */
-
-/* Board NAND Info */
-#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
-							/* to access nand at */
-							/* CS0 */
-#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
-							/* devices */
-#define CONFIG_SYS_NAND_MAX_OOBFREE	2
-#define CONFIG_SYS_NAND_MAX_ECCPOS	56
-
-/* needed for ubi */
-
-/* Environment information (this is the common part) */
-
-
-/* hang() the board on panic() */
-
-/* environment placement (for NAND), is different for FLASHCARD but does not
- * harm there */
-#define CONFIG_ENV_RANGE		(384 << 10) /* allow badblocks in env */
-
-/* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
- * value can not be used here! */
-#define CONFIG_LOADADDR		0x82000000
-
-#define CONFIG_COMMON_ENV_SETTINGS \
-	"console=ttyO2,115200n8\0" \
-	"mmcdev=0\0" \
-	"vram=3M\0" \
-	"defaultdisplay=lcd\0" \
-	"kernelopts=mtdoops.mtddev=3\0" \
-	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
-	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
-	"commonargs=" \
-		"setenv bootargs console=${console} " \
-		"${mtdparts} " \
-		"${kernelopts} " \
-		"vt.global_cursor_default=0 " \
-		"vram=${vram} " \
-		"omapdss.def_disp=${defaultdisplay}\0"
-
-#define CONFIG_BOOTCOMMAND "run autoboot"
-
-/* specific environment settings for different use cases
- * FLASHCARD: used to run a rdimage from sdcard to program the device
- * 'NORMAL': used to boot kernel from sdcard, nand, ...
- *
- * The main aim for the FLASHCARD skin is to have an embedded environment
- * which will not be influenced by any data already on the device.
- */
-#ifdef CONFIG_FLASHCARD
-/* the rdaddr is 16 MiB before the loadaddr */
-#define CONFIG_ENV_RDADDR	"rdaddr=0x81000000\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	CONFIG_COMMON_ENV_SETTINGS \
-	CONFIG_ENV_RDADDR \
-	"autoboot=" \
-	"run commonargs; " \
-	"setenv bootargs ${bootargs} " \
-		"flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
-		"rdinit=/sbin/init; " \
-	"mmc dev ${mmcdev}; mmc rescan; " \
-	"fatload mmc ${mmcdev} ${loadaddr} uImage; " \
-	"fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
-	"bootm ${loadaddr} ${rdaddr}\0"
-
-#else /* CONFIG_FLASHCARD */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	CONFIG_COMMON_ENV_SETTINGS \
-	"mmcargs=" \
-		"run commonargs; " \
-		"setenv bootargs ${bootargs} " \
-		"root=/dev/mmcblk0p2 " \
-		"rootwait " \
-		"rw\0" \
-	"nandargs=" \
-		"run commonargs; " \
-		"setenv bootargs ${bootargs} " \
-		"root=ubi0:root " \
-		"ubi.mtd=7 " \
-		"rootfstype=ubifs " \
-		"ro\0" \
-	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
-	"bootscript=echo Running bootscript from mmc ...; " \
-		"source ${loadaddr}\0" \
-	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
-	"mmcboot=echo Booting from mmc ...; " \
-		"run mmcargs; " \
-		"bootm ${loadaddr}\0" \
-	"loaduimage_ubi=ubi part ubi; " \
-		"ubifsmount ubi:root; " \
-		"ubifsload ${loadaddr} /boot/uImage\0" \
-	"loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
-	"nandboot=echo Booting from nand ...; " \
-		"run nandargs; " \
-		"run loaduimage_nand; " \
-		"bootm ${loadaddr}\0" \
-	"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
-			"if run loadbootscript; then " \
-				"run bootscript; " \
-			"else " \
-				"if run loaduimage; then " \
-					"run mmcboot; " \
-				"else run nandboot; " \
-				"fi; " \
-			"fi; " \
-		"else run nandboot; fi\0"
-
-#endif /* CONFIG_FLASHCARD */
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
-
-#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0 + 0x02000000)
-
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV			2 /* Divisor: 2^(PTV+1) => 8 */
-
-/*  Physical Memory Map  */
-#define PHYS_SDRAM_1			OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2			OMAP34XX_SDRC_CS1
-
-/* NAND and environment organization  */
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE	0x800
-#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
-						CONFIG_SYS_INIT_RAM_SIZE - \
-						GENERATED_GBL_DATA_SIZE)
-
-/* Defines for SPL */
-
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME        "u-boot.img"
-
-#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
-					 CONFIG_SPL_TEXT_BASE)
-
-#define CONFIG_SPL_BSS_START_ADDR	0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
-#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
-
-/* NAND boot config */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT	64
-#define CONFIG_SYS_NAND_PAGE_SIZE	2048
-#define CONFIG_SYS_NAND_OOBSIZE		64
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
-					 13, 14, 16, 17, 18, 19, 20, 21, 22, \
-					 23, 24, 25, 26, 27, 28, 30, 31, 32, \
-					 33, 34, 35, 36, 37, 38, 39, 40, 41, \
-					 42, 44, 45, 46, 47, 48, 49, 50, 51, \
-					 52, 53, 54, 55, 56}
-
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	13
-#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
-
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x20000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x100000
-
-#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
-#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000	/* 1 MB */
-
-#endif /* __CONFIG_H */