diff mbox series

[v3,2/2] riscv: timer: Add support for an early timer

Message ID 20210110124254.16312-2-pragnesh.patel@sifive.com
State Superseded
Delegated to: Andes
Headers show
Series [v3,1/2] trace: select TIMER_EARLY to avoid infinite recursion | expand

Commit Message

Pragnesh Patel Jan. 10, 2021, 12:42 p.m. UTC
Added support for timer_early_get_count() and timer_early_get_rate()
This is mostly useful in tracing.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
---

Changes in v3:
- Add IS_ENABLED(CONFIG_TIMER_EARLY) for timer_early_get_rate()
  and timer_early_get_count() functions.

Changes in v2:
- make u-boot compile for qemu (include/configs/qemu-riscv.h)

 drivers/timer/andes_plmt_timer.c   | 21 ++++++++++++++++++++-
 drivers/timer/riscv_timer.c        | 21 ++++++++++++++++++++-
 drivers/timer/sifive_clint_timer.c | 21 ++++++++++++++++++++-
 include/configs/ax25-ae350.h       |  5 +++++
 include/configs/qemu-riscv.h       |  5 +++++
 include/configs/sifive-fu540.h     |  5 +++++
 6 files changed, 75 insertions(+), 3 deletions(-)

Comments

Rick Chen Jan. 11, 2021, 2:33 a.m. UTC | #1
> From: Pragnesh Patel [mailto:pragnesh.patel@sifive.com]
> Sent: Sunday, January 10, 2021 8:43 PM
> To: u-boot@lists.denx.de
> Cc: atish.patra@wdc.com; palmerdabbelt@google.com; bmeng.cn@gmail.com; paul.walmsley@sifive.com; anup.patel@wdc.com; sagar.kadam@sifive.com; Rick Jian-Zhi Chen(陳建志); Pragnesh Patel; Palmer Dabbelt; Sean Anderson; Simon Glass
> Subject: [PATCH v3 2/2] riscv: timer: Add support for an early timer
>
> Added support for timer_early_get_count() and timer_early_get_rate()
> This is mostly useful in tracing.
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> ---
>
> Changes in v3:
> - Add IS_ENABLED(CONFIG_TIMER_EARLY) for timer_early_get_rate()
>   and timer_early_get_count() functions.

Reviewed-by: Rick Chen <rick@andestech.com>
Rick Chen Jan. 12, 2021, 2 a.m. UTC | #2
Hi Pragnesh

> > From: Pragnesh Patel [mailto:pragnesh.patel@sifive.com]
> > Sent: Sunday, January 10, 2021 8:43 PM
> > To: u-boot@lists.denx.de
> > Cc: atish.patra@wdc.com; palmerdabbelt@google.com; bmeng.cn@gmail.com; paul.walmsley@sifive.com; anup.patel@wdc.com; sagar.kadam@sifive.com; Rick Jian-Zhi Chen(陳建志); Pragnesh Patel; Palmer Dabbelt; Sean Anderson; Simon Glass
> > Subject: [PATCH v3 2/2] riscv: timer: Add support for an early timer
> >
> > Added support for timer_early_get_count() and timer_early_get_rate()
> > This is mostly useful in tracing.
> >
> > Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> > ---
> >
> > Changes in v3:
> > - Add IS_ENABLED(CONFIG_TIMER_EARLY) for timer_early_get_rate()
> >   and timer_early_get_count() functions.
>
> Reviewed-by: Rick Chen <rick@andestech.com>

I am trying to merge to mainline, but it conflict with master.
Please rebase again,

Applying: trace: select TIMER_EARLY to avoid infinite recursion
Applying: riscv: timer: Add support for an early timer
error: patch failed: drivers/timer/andes_plmt_timer.c:17
error: drivers/timer/andes_plmt_timer.c: patch does not apply
error: patch failed: drivers/timer/sifive_clint_timer.c:14
error: drivers/timer/sifive_clint_timer.c: patch does not apply
Patch failed at 0002 riscv: timer: Add support for an early timer
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

Thanks,
Rick
Pragnesh Patel Jan. 17, 2021, 12:39 p.m. UTC | #3
Hi Rick

On Tue, Jan 12, 2021 at 7:30 AM Rick Chen <rickchen36@gmail.com> wrote:
>
> Hi Pragnesh
>
> > > From: Pragnesh Patel [mailto:pragnesh.patel@sifive.com]
> > > Sent: Sunday, January 10, 2021 8:43 PM
> > > To: u-boot@lists.denx.de
> > > Cc: atish.patra@wdc.com; palmerdabbelt@google.com; bmeng.cn@gmail.com; paul.walmsley@sifive.com; anup.patel@wdc.com; sagar.kadam@sifive.com; Rick Jian-Zhi Chen(陳建志); Pragnesh Patel; Palmer Dabbelt; Sean Anderson; Simon Glass
> > > Subject: [PATCH v3 2/2] riscv: timer: Add support for an early timer
> > >
> > > Added support for timer_early_get_count() and timer_early_get_rate()
> > > This is mostly useful in tracing.
> > >
> > > Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> > > ---
> > >
> > > Changes in v3:
> > > - Add IS_ENABLED(CONFIG_TIMER_EARLY) for timer_early_get_rate()
> > >   and timer_early_get_count() functions.
> >
> > Reviewed-by: Rick Chen <rick@andestech.com>
>
> I am trying to merge to mainline, but it conflict with master.
> Please rebase again,
>
> Applying: trace: select TIMER_EARLY to avoid infinite recursion
> Applying: riscv: timer: Add support for an early timer
> error: patch failed: drivers/timer/andes_plmt_timer.c:17
> error: drivers/timer/andes_plmt_timer.c: patch does not apply
> error: patch failed: drivers/timer/sifive_clint_timer.c:14
> error: drivers/timer/sifive_clint_timer.c: patch does not apply
> Patch failed at 0002 riscv: timer: Add support for an early timer
> The copy of the patch that failed is found in: .git/rebase-apply/patch
> When you have resolved this problem, run "git am --continue".
> If you prefer to skip this patch, run "git am --skip" instead.
> To restore the original branch and stop patching, run "git am --abort".

Will rebase and send again.

>
> Thanks,
> Rick
diff mbox series

Patch

diff --git a/drivers/timer/andes_plmt_timer.c b/drivers/timer/andes_plmt_timer.c
index cec86718c7..ce4040d76d 100644
--- a/drivers/timer/andes_plmt_timer.c
+++ b/drivers/timer/andes_plmt_timer.c
@@ -17,11 +17,30 @@ 
 /* mtime register */
 #define MTIME_REG(base)			((ulong)(base))
 
-static u64 andes_plmt_get_count(struct udevice *dev)
+static u64 notrace andes_plmt_get_count(struct udevice *dev)
 {
 	return readq((void __iomem *)MTIME_REG(dev->priv));
 }
 
+#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
+/**
+ * timer_early_get_rate() - Get the timer rate before driver model
+ */
+unsigned long notrace timer_early_get_rate(void)
+{
+	return RISCV_MMODE_TIMER_FREQ;
+}
+
+/**
+ * timer_early_get_count() - Get the timer count before driver model
+ *
+ */
+u64 notrace timer_early_get_count(void)
+{
+	return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
+}
+#endif
+
 static const struct timer_ops andes_plmt_ops = {
 	.get_count = andes_plmt_get_count,
 };
diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index 21ae184057..3627ed79b8 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -16,7 +16,7 @@ 
 #include <timer.h>
 #include <asm/csr.h>
 
-static u64 riscv_timer_get_count(struct udevice *dev)
+static u64 notrace riscv_timer_get_count(struct udevice *dev)
 {
 	__maybe_unused u32 hi, lo;
 
@@ -31,6 +31,25 @@  static u64 riscv_timer_get_count(struct udevice *dev)
 	return ((u64)hi << 32) | lo;
 }
 
+#if CONFIG_IS_ENABLED(RISCV_SMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
+/**
+ * timer_early_get_rate() - Get the timer rate before driver model
+ */
+unsigned long notrace timer_early_get_rate(void)
+{
+	return RISCV_SMODE_TIMER_FREQ;
+}
+
+/**
+ * timer_early_get_count() - Get the timer count before driver model
+ *
+ */
+u64 notrace timer_early_get_count(void)
+{
+	return riscv_timer_get_count(NULL);
+}
+#endif
+
 static int riscv_timer_probe(struct udevice *dev)
 {
 	struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
diff --git a/drivers/timer/sifive_clint_timer.c b/drivers/timer/sifive_clint_timer.c
index 00ce0f08d6..2e902feb61 100644
--- a/drivers/timer/sifive_clint_timer.c
+++ b/drivers/timer/sifive_clint_timer.c
@@ -14,11 +14,30 @@ 
 /* mtime register */
 #define MTIME_REG(base)			((ulong)(base) + 0xbff8)
 
-static u64 sifive_clint_get_count(struct udevice *dev)
+static u64 notrace sifive_clint_get_count(struct udevice *dev)
 {
 	return readq((void __iomem *)MTIME_REG(dev->priv));
 }
 
+#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
+/**
+ * timer_early_get_rate() - Get the timer rate before driver model
+ */
+unsigned long notrace timer_early_get_rate(void)
+{
+	return RISCV_MMODE_TIMER_FREQ;
+}
+
+/**
+ * timer_early_get_count() - Get the timer count before driver model
+ *
+ */
+u64 notrace timer_early_get_count(void)
+{
+	return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
+}
+#endif
+
 static const struct timer_ops sifive_clint_ops = {
 	.get_count = sifive_clint_get_count,
 };
diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h
index b2606e794d..bd9c371f83 100644
--- a/include/configs/ax25-ae350.h
+++ b/include/configs/ax25-ae350.h
@@ -17,6 +17,11 @@ 
 #endif
 #endif
 
+#define RISCV_MMODE_TIMERBASE           0xe6000000
+#define RISCV_MMODE_TIMER_FREQ          60000000
+
+#define RISCV_SMODE_TIMER_FREQ          60000000
+
 /*
  * CPU and Board Configuration Options
  */
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index a2f33587c2..5291de83f8 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -29,6 +29,11 @@ 
 
 #define CONFIG_STANDALONE_LOAD_ADDR	0x80200000
 
+#define RISCV_MMODE_TIMERBASE		0x2000000
+#define RISCV_MMODE_TIMER_FREQ		1000000
+
+#define RISCV_SMODE_TIMER_FREQ		1000000
+
 /* Environment options */
 
 #ifndef CONFIG_SPL_BUILD
diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
index c1c79db147..0d69d1c548 100644
--- a/include/configs/sifive-fu540.h
+++ b/include/configs/sifive-fu540.h
@@ -36,6 +36,11 @@ 
 
 #define CONFIG_STANDALONE_LOAD_ADDR	0x80200000
 
+#define RISCV_MMODE_TIMERBASE		0x2000000
+#define RISCV_MMODE_TIMER_FREQ		1000000
+
+#define RISCV_SMODE_TIMER_FREQ		1000000
+
 /* Environment options */
 
 #ifndef CONFIG_SPL_BUILD