From patchwork Thu Dec 17 17:28:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 1417809 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=fRlg0Qm7; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Cxf9G5rzNz9sWK for ; Fri, 18 Dec 2020 04:28:28 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0CB4782B2A; Thu, 17 Dec 2020 18:28:18 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="fRlg0Qm7"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id B9AAF82B96; Thu, 17 Dec 2020 18:28:16 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0201D82B18 for ; Thu, 17 Dec 2020 18:28:12 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=lokeshvutla@ti.com Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BHHSBYt030193 for ; Thu, 17 Dec 2020 11:28:11 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608226091; bh=/UDWJEIV39jTQt+o/OzkgeOHHudVnD8OB7LLktk6ONc=; h=From:To:CC:Subject:Date; b=fRlg0Qm7bFPHZTUXB2k0OKXPwNuo2P1YpciY4mjDtP8Q8r3e5D56tFIYPG18eZGwj WOC8nConzCnBiB9We7OEzXNHKpp6CTDj/I2ERaMFKV6p/4TcT4+ACfWotU8/Ie+sPv sGYXVt9SlBrZvkymoRQ/TuheEFIZJy/Qaj4QfrSY= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BHHSBIP111896 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Thu, 17 Dec 2020 11:28:11 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 17 Dec 2020 11:28:10 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 17 Dec 2020 11:28:10 -0600 Received: from lokesh-ssd.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BHHS8p9107221; Thu, 17 Dec 2020 11:28:09 -0600 From: Lokesh Vutla To: CC: Lokesh Vutla , Sekhar Nori Subject: [PATCH] board: ti: k2g: Add support for K2G ICE with 1GHz Silicon Date: Thu, 17 Dec 2020 22:58:07 +0530 Message-ID: <20201217172807.25457-1-lokeshvutla@ti.com> X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Add board detection support for K2G ICE with FlagChip 1GHz silicon. Signed-off-by: Lokesh Vutla --- board/ti/ks2_evm/board.c | 4 ++-- board/ti/ks2_evm/board.h | 8 ++++++++ board/ti/ks2_evm/board_k2g.c | 7 +++++-- board/ti/ks2_evm/ddr3_k2g.c | 2 +- board/ti/ks2_evm/mux-k2g.h | 2 +- include/configs/k2g_evm.h | 2 ++ 6 files changed, 19 insertions(+), 6 deletions(-) diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index c7be540028..53bc12791d 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -48,11 +48,11 @@ int dram_init(void) gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); #if defined(CONFIG_TI_AEMIF) - if (!board_is_k2g_ice()) + if (!(board_is_k2g_ice() || board_is_k2g_i1())) aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); #endif - if (!board_is_k2g_ice()) { + if (!(board_is_k2g_ice() || board_is_k2g_i1())) { if (ddr3_size) ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size); else diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h index d0cfbf5a75..93fc3887f4 100644 --- a/board/ti/ks2_evm/board.h +++ b/board/ti/ks2_evm/board.h @@ -25,6 +25,10 @@ static inline int board_is_k2g_ice(void) { return board_ti_is("66AK2GIC"); } +static inline int board_is_k2g_i1(void) +{ + return board_ti_is("66AK2GI1"); +} #else static inline int board_is_k2g_gp(void) { @@ -34,6 +38,10 @@ static inline int board_is_k2g_ice(void) { return false; } +static inline int board_is_k2g_i1(void) +{ + return false; +} #endif void spl_init_keystone_plls(void); diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index a71024bcbc..2be86d6d26 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -248,7 +248,8 @@ int board_fit_config_name_match(const char *name) else if (!strcmp(name, "keystone-k2g-evm") && (board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1"))) return 0; - else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC")) + else if (!strcmp(name, "keystone-k2g-ice") && + (board_ti_is("66AK2GIC") || board_is_k2g_i1())) return 0; else return -1; @@ -322,7 +323,7 @@ int embedded_dtb_select(void) BIT(9)); setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET, BIT(9)); - } else if (board_is_k2g_ice()) { + } else if (board_is_k2g_ice() || board_is_k2g_i1()) { /* GBE Phy workaround. For Phy to latch the input * configuration, a GPIO reset is asserted at the * Phy reset pin to latch configuration correctly after SoC @@ -364,6 +365,8 @@ int board_late_init(void) env_set("board_name", "66AK2GG1\0"); else if (board_is_k2g_ice()) env_set("board_name", "66AK2GIC\0"); + else if (board_is_k2g_i1()) + env_set("board_name", "66AK2GI1\0"); #endif return 0; } diff --git a/board/ti/ks2_evm/ddr3_k2g.c b/board/ti/ks2_evm/ddr3_k2g.c index 563c5e9950..3000d7245e 100644 --- a/board/ti/ks2_evm/ddr3_k2g.c +++ b/board/ti/ks2_evm/ddr3_k2g.c @@ -174,7 +174,7 @@ u32 ddr3_init(void) } else if (board_is_k2g_gp()) { ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g); ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g); - } else if (board_is_k2g_ice()) { + } else if (board_is_k2g_ice() || board_is_k2g_i1()) { ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_512mb); ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_512mb); } diff --git a/board/ti/ks2_evm/mux-k2g.h b/board/ti/ks2_evm/mux-k2g.h index 3ecf571c5c..fa6c92cbdf 100644 --- a/board/ti/ks2_evm/mux-k2g.h +++ b/board/ti/ks2_evm/mux-k2g.h @@ -377,7 +377,7 @@ void k2g_mux_config(void) configure_pin_mux(k2g_generic_pin_cfg); } else if (board_is_k2g_gp() || board_is_k2g_g1()) { configure_pin_mux(k2g_evm_pin_cfg); - } else if (board_is_k2g_ice()) { + } else if (board_is_k2g_ice() || board_is_k2g_i1()) { configure_pin_mux(k2g_ice_evm_pin_cfg); } else { puts("Unknown board, cannot configure pinmux."); diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index 83466b9e0c..4471eb4f6a 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -35,6 +35,8 @@ "setenv name_fdt keystone-k2g-evm.dtb; " \ "else if test $board_name = 66AK2GIC; then " \ "setenv name_fdt keystone-k2g-ice.dtb; " \ + "else if test $board_name = 66AK2GI1; then " \ + "setenv name_fdt keystone-k2g-ice.dtb; " \ "else if test $name_fdt = undefined; then " \ "echo WARNING: Could not determine device tree to use;"\ "fi;fi;fi;fi; setenv fdtfile ${name_fdt}\0" \