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d="scan'208";a="106311312" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 05 Dec 2020 03:03:49 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Sat, 5 Dec 2020 03:03:49 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Sat, 5 Dec 2020 03:03:42 -0700 From: Eugen Hristev To: CC: , , Subject: [PATCH v2 01/34] ARM: dts: sama7g5: add initial DT for sama7g5 SoC Date: Sat, 5 Dec 2020 12:02:43 +0200 Message-ID: <20201205100316.179531-2-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201205100316.179531-1-eugen.hristev@microchip.com> References: <20201205100316.179531-1-eugen.hristev@microchip.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Add initial basic devicetree for sama7g5 SoC Signed-off-by: Eugen Hristev --- arch/arm/dts/sama7g5.dtsi | 65 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 arch/arm/dts/sama7g5.dtsi diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi new file mode 100644 index 0000000000..24b6f90957 --- /dev/null +++ b/arch/arm/dts/sama7g5.dtsi @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sama7g5.dtsi - Device Tree Include file for SAMA7G5 SoC. + * + * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries + * + * Author: Eugen Hristev + * Author: Claudiu Beznea + * + */ + +#include "skeleton.dtsi" + +/ { + model = "Microchip SAMA7G5 family SoC"; + compatible = "microchip,sama7g5"; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + mck: mck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + sdmmc1: sdio-host@e1208000 { + compatible = "microchip,sama7g5-sdhci"; + reg = <0xe1208000 0x300>; + clocks = <&mck>, <&mck>, <&mck>; + clock-names = "hclock", "multclk", "baseclk"; + status = "disabled"; + }; + + uart0: serial@e1824200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xe1824200 0x200>; + clocks = <&mck>; + clock-names = "usart"; + status = "disabled"; + }; + }; + }; +};