diff mbox series

[3/3] arm64: dts: imx8mm-beacon: Re-sync dts file with Linux 5.10-rc6

Message ID 20201204232747.223325-3-aford173@gmail.com
State Accepted
Commit 1170d2b759096af0e7ba6ffaf6abde286a7d6595
Delegated to: Stefano Babic
Headers show
Series [1/3] imx: imx8mm: Update clock bindings header | expand

Commit Message

Adam Ford Dec. 4, 2020, 11:27 p.m. UTC 
There have been some updates to the device trees, so re-sync.

Signed-off-by: Adam Ford <aford173@gmail.com>

Comments

Peng Fan Dec. 7, 2020, 2:11 a.m. UTC | #1 
> Subject: [PATCH 3/3] arm64: dts: imx8mm-beacon: Re-sync dts file with Linux
> 5.10-rc6
> 
> There have been some updates to the device trees, so re-sync.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>


Acked-by: Peng Fan <peng.fan@nxp.com>

> 
> diff --git a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
> b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
> index baa5f997d0..d6b9dedd16 100644
> --- a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
> +++ b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
> @@ -10,19 +10,19 @@
>  		led0 {
>  			label = "gen_led0";
>  			gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
> -			default-state = "none";
> +			default-state = "off";
>  		};
> 
>  		led1 {
>  			label = "gen_led1";
>  			gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
> -			default-state = "none";
> +			default-state = "off";
>  		};
> 
>  		led2 {
>  			label = "gen_led2";
>  			gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
> -			default-state = "none";
> +			default-state = "off";
>  		};
> 
>  		led3 {
> @@ -70,7 +70,7 @@
>  &ecspi2 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_espi2>;
> -	cs-gpios = <&gpio5 9 0>;
> +	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
>  	status = "okay";
> 
>  	eeprom@0 {
> @@ -210,7 +210,7 @@
>  		>;
>  	};
> 
> -	pinctrl_pcal6414: pcal6414-gpio {
> +	pinctrl_pcal6414: pcal6414-gpiogrp {
>  		fsl,pins = <
>  			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x19
>  		>;
> @@ -240,7 +240,7 @@
>  		>;
>  	};
> 
> -	pinctrl_usdhc2_gpio: usdhc2grpgpio {
> +	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
>  		fsl,pins = <
>  			MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B	0x41
>  			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
> @@ -259,7 +259,7 @@
>  		>;
>  	};
> 
> -	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> +	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
>  		fsl,pins = <
>  			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x194
>  			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d4
> @@ -271,7 +271,7 @@
>  		>;
>  	};
> 
> -	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> +	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
>  		fsl,pins = <
>  			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x196
>  			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d6
> diff --git a/arch/arm/dts/imx8mm-beacon-som.dtsi
> b/arch/arm/dts/imx8mm-beacon-som.dtsi
> index 801bd02eae..b88c3c99b0 100644
> --- a/arch/arm/dts/imx8mm-beacon-som.dtsi
> +++ b/arch/arm/dts/imx8mm-beacon-som.dtsi
> @@ -24,6 +24,26 @@
>  	cpu-supply = <&buck2_reg>;
>  };
> 
> +&ddrc {
> +	operating-points-v2 = <&ddrc_opp_table>;
> +
> +	ddrc_opp_table: opp-table {
> +		compatible = "operating-points-v2";
> +
> +		opp-25M {
> +			opp-hz = /bits/ 64 <25000000>;
> +		};
> +
> +		opp-100M {
> +			opp-hz = /bits/ 64 <100000000>;
> +		};
> +
> +		opp-750M {
> +			opp-hz = /bits/ 64 <750000000>;
> +		};
> +	};
> +};
> +
>  &fec1 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_fec1>;
> @@ -52,9 +72,10 @@
>  	pmic@4b {
>  		compatible = "rohm,bd71847";
>  		reg = <0x4b>;
> +		pinctrl-names = "default";
>  		pinctrl-0 = <&pinctrl_pmic>;
>  		interrupt-parent = <&gpio1>;
> -		interrupts = <3 GPIO_ACTIVE_LOW>;
> +		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
>  		rohm,reset-snvs-powered;
> 
>  		regulators {
> @@ -116,7 +137,7 @@
> 
>  			ldo1_reg: LDO1 {
>  				regulator-name = "ldo1";
> -				regulator-min-microvolt = <3000000>;
> +				regulator-min-microvolt = <1600000>;
>  				regulator-max-microvolt = <3300000>;
>  				regulator-boot-on;
>  				regulator-always-on;
> @@ -124,7 +145,7 @@
> 
>  			ldo2_reg: LDO2 {
>  				regulator-name = "ldo2";
> -				regulator-min-microvolt = <900000>;
> +				regulator-min-microvolt = <800000>;
>  				regulator-max-microvolt = <900000>;
>  				regulator-boot-on;
>  				regulator-always-on;
> @@ -164,7 +185,7 @@
>  	status = "okay";
> 
>  	eeprom@50 {
> -		compatible = "microchip, at24c64d", "atmel,24c64";
> +		compatible = "microchip,24c64", "atmel,24c64";
>  		pagesize = <32>;
>  		read-only;	/* Manufacturing EEPROM programmed at factory */
>  		reg = <0x50>;
> @@ -190,6 +211,7 @@
>  		host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
>  		device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
>  		clocks = <&osc_32k>;
> +		max-speed = <4000000>;
>  		clock-names = "extclk";
>  	};
>  };
> @@ -270,9 +292,9 @@
>  			>;
>  		};
> 
> -		pinctrl_pmic: pmicirq {
> +		pinctrl_pmic: pmicirqgrp {
>  			fsl,pins = <
> -				MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x41
> +				MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x141
>  			>;
>  		};
> 
> @@ -289,7 +311,7 @@
>  			>;
>  		};
> 
> -		pinctrl_usdhc1_gpio: usdhc1grpgpio {
> +		pinctrl_usdhc1_gpio: usdhc1gpiogrp {
>  			fsl,pins = <
>  				MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41
>  			>;
> @@ -306,7 +328,7 @@
>  			>;
>  		};
> 
> -		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> +		pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
>  			fsl,pins = <
>  				MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
> 	0x194
>  				MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
> 	0x1d4
> @@ -317,7 +339,7 @@
>  			>;
>  		};
> 
> -		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> +		pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
>  			fsl,pins = <
>  				MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
> 	0x196
>  				MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
> 	0x1d6
> @@ -344,7 +366,7 @@
>  			>;
>  		};
> 
> -		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
> +		pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
>  			fsl,pins = <
>  				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK
> 	0x194
>  				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD
> 	0x1d4
> @@ -360,7 +382,7 @@
>  			>;
>  		};
> 
> -		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
> +		pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
>  			fsl,pins = <
>  				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK
> 	0x196
>  				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD
> 	0x1d6
> --
> 2.25.1
Stefano Babic Dec. 26, 2020, 3:53 p.m. UTC | #2 
> There have been some updates to the device trees, so re-sync.
> Signed-off-by: Adam Ford <aford173@gmail.com>
> Acked-by: Peng Fan <peng.fan@nxp.com>
> diff --git a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
> index baa5f997d0..d6b9dedd16 100644
> --- a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
> +++ b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
> @@ -10,19 +10,19 @@
>  		led0 {
>  			label = "gen_led0";
>  			gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
> -			default-state = "none";
> +			default-state = "off";
>  		};
>  
>  		led1 {
>  			label = "gen_led1";
>  			gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
> -			default-state = "none";
> +			default-state = "off";
>  		};
>  
>  		led2 {
>  			label = "gen_led2";
>  			gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
> -			default-state = "none";
> +			default-state = "off";
>  		};
>  
>  		led3 {
> @@ -70,7 +70,7 @@
>  &ecspi2 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_espi2>;
> -	cs-gpios = <&gpio5 9 0>;
> +	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
>  	status = "okay";
>  
>  	eeprom@0 {
> @@ -210,7 +210,7 @@
>  		>;
>  	};
>  
> -	pinctrl_pcal6414: pcal6414-gpio {
> +	pinctrl_pcal6414: pcal6414-gpiogrp {
>  		fsl,pins = <
>  			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x19
>  		>;
> @@ -240,7 +240,7 @@
>  		>;
>  	};
>  
> -	pinctrl_usdhc2_gpio: usdhc2grpgpio {
> +	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
>  		fsl,pins = <
>  			MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B	0x41
>  			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
> @@ -259,7 +259,7 @@
>  		>;
>  	};
>  
> -	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> +	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
>  		fsl,pins = <
>  			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x194
>  			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d4
> @@ -271,7 +271,7 @@
>  		>;
>  	};
>  
> -	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> +	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
>  		fsl,pins = <
>  			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x196
>  			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d6
> diff --git a/arch/arm/dts/imx8mm-beacon-som.dtsi b/arch/arm/dts/imx8mm-beacon-som.dtsi
> index 801bd02eae..b88c3c99b0 100644
> --- a/arch/arm/dts/imx8mm-beacon-som.dtsi
> +++ b/arch/arm/dts/imx8mm-beacon-som.dtsi
> @@ -24,6 +24,26 @@
>  	cpu-supply = <&buck2_reg>;
>  };
>  
> +&ddrc {
> +	operating-points-v2 = <&ddrc_opp_table>;
> +
> +	ddrc_opp_table: opp-table {
> +		compatible = "operating-points-v2";
> +
> +		opp-25M {
> +			opp-hz = /bits/ 64 <25000000>;
> +		};
> +
> +		opp-100M {
> +			opp-hz = /bits/ 64 <100000000>;
> +		};
> +
> +		opp-750M {
> +			opp-hz = /bits/ 64 <750000000>;
> +		};
> +	};
> +};
> +
>  &fec1 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_fec1>;
> @@ -52,9 +72,10 @@
>  	pmic@4b {
>  		compatible = "rohm,bd71847";
>  		reg = <0x4b>;
> +		pinctrl-names = "default";
>  		pinctrl-0 = <&pinctrl_pmic>;
>  		interrupt-parent = <&gpio1>;
> -		interrupts = <3 GPIO_ACTIVE_LOW>;
> +		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
>  		rohm,reset-snvs-powered;
>  
>  		regulators {
> @@ -116,7 +137,7 @@
>  
>  			ldo1_reg: LDO1 {
>  				regulator-name = "ldo1";
> -				regulator-min-microvolt = <3000000>;
> +				regulator-min-microvolt = <1600000>;
>  				regulator-max-microvolt = <3300000>;
>  				regulator-boot-on;
>  				regulator-always-on;
> @@ -124,7 +145,7 @@
>  
>  			ldo2_reg: LDO2 {
>  				regulator-name = "ldo2";
> -				regulator-min-microvolt = <900000>;
> +				regulator-min-microvolt = <800000>;
>  				regulator-max-microvolt = <900000>;
>  				regulator-boot-on;
>  				regulator-always-on;
> @@ -164,7 +185,7 @@
>  	status = "okay";
>  
>  	eeprom@50 {
> -		compatible = "microchip, at24c64d", "atmel,24c64";
> +		compatible = "microchip,24c64", "atmel,24c64";
>  		pagesize = <32>;
>  		read-only;	/* Manufacturing EEPROM programmed at factory */
>  		reg = <0x50>;
> @@ -190,6 +211,7 @@
>  		host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
>  		device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
>  		clocks = <&osc_32k>;
> +		max-speed = <4000000>;
>  		clock-names = "extclk";
>  	};
>  };
> @@ -270,9 +292,9 @@
>  			>;
>  		};
>  
> -		pinctrl_pmic: pmicirq {
> +		pinctrl_pmic: pmicirqgrp {
>  			fsl,pins = <
> -				MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x41
> +				MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x141
>  			>;
>  		};
>  
> @@ -289,7 +311,7 @@
>  			>;
>  		};
>  
> -		pinctrl_usdhc1_gpio: usdhc1grpgpio {
> +		pinctrl_usdhc1_gpio: usdhc1gpiogrp {
>  			fsl,pins = <
>  				MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41
>  			>;
> @@ -306,7 +328,7 @@
>  			>;
>  		};
>  
> -		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> +		pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
>  			fsl,pins = <
>  				MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
>  				MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
> @@ -317,7 +339,7 @@
>  			>;
>  		};
>  
> -		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> +		pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
>  			fsl,pins = <
>  				MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
>  				MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
> @@ -344,7 +366,7 @@
>  			>;
>  		};
>  
> -		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
> +		pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
>  			fsl,pins = <
>  				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
>  				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
> @@ -360,7 +382,7 @@
>  			>;
>  		};
>  
> -		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
> +		pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
>  			fsl,pins = <
>  				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
>  				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic
diff mbox series

Patch

diff --git a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
index baa5f997d0..d6b9dedd16 100644
--- a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
+++ b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
@@ -10,19 +10,19 @@ 
 		led0 {
 			label = "gen_led0";
 			gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
-			default-state = "none";
+			default-state = "off";
 		};
 
 		led1 {
 			label = "gen_led1";
 			gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
-			default-state = "none";
+			default-state = "off";
 		};
 
 		led2 {
 			label = "gen_led2";
 			gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
-			default-state = "none";
+			default-state = "off";
 		};
 
 		led3 {
@@ -70,7 +70,7 @@ 
 &ecspi2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_espi2>;
-	cs-gpios = <&gpio5 9 0>;
+	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
 	status = "okay";
 
 	eeprom@0 {
@@ -210,7 +210,7 @@ 
 		>;
 	};
 
-	pinctrl_pcal6414: pcal6414-gpio {
+	pinctrl_pcal6414: pcal6414-gpiogrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x19
 		>;
@@ -240,7 +240,7 @@ 
 		>;
 	};
 
-	pinctrl_usdhc2_gpio: usdhc2grpgpio {
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B	0x41
 			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
@@ -259,7 +259,7 @@ 
 		>;
 	};
 
-	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x194
 			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d4
@@ -271,7 +271,7 @@ 
 		>;
 	};
 
-	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x196
 			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d6
diff --git a/arch/arm/dts/imx8mm-beacon-som.dtsi b/arch/arm/dts/imx8mm-beacon-som.dtsi
index 801bd02eae..b88c3c99b0 100644
--- a/arch/arm/dts/imx8mm-beacon-som.dtsi
+++ b/arch/arm/dts/imx8mm-beacon-som.dtsi
@@ -24,6 +24,26 @@ 
 	cpu-supply = <&buck2_reg>;
 };
 
+&ddrc {
+	operating-points-v2 = <&ddrc_opp_table>;
+
+	ddrc_opp_table: opp-table {
+		compatible = "operating-points-v2";
+
+		opp-25M {
+			opp-hz = /bits/ 64 <25000000>;
+		};
+
+		opp-100M {
+			opp-hz = /bits/ 64 <100000000>;
+		};
+
+		opp-750M {
+			opp-hz = /bits/ 64 <750000000>;
+		};
+	};
+};
+
 &fec1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec1>;
@@ -52,9 +72,10 @@ 
 	pmic@4b {
 		compatible = "rohm,bd71847";
 		reg = <0x4b>;
+		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_pmic>;
 		interrupt-parent = <&gpio1>;
-		interrupts = <3 GPIO_ACTIVE_LOW>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 		rohm,reset-snvs-powered;
 
 		regulators {
@@ -116,7 +137,7 @@ 
 
 			ldo1_reg: LDO1 {
 				regulator-name = "ldo1";
-				regulator-min-microvolt = <3000000>;
+				regulator-min-microvolt = <1600000>;
 				regulator-max-microvolt = <3300000>;
 				regulator-boot-on;
 				regulator-always-on;
@@ -124,7 +145,7 @@ 
 
 			ldo2_reg: LDO2 {
 				regulator-name = "ldo2";
-				regulator-min-microvolt = <900000>;
+				regulator-min-microvolt = <800000>;
 				regulator-max-microvolt = <900000>;
 				regulator-boot-on;
 				regulator-always-on;
@@ -164,7 +185,7 @@ 
 	status = "okay";
 
 	eeprom@50 {
-		compatible = "microchip, at24c64d", "atmel,24c64";
+		compatible = "microchip,24c64", "atmel,24c64";
 		pagesize = <32>;
 		read-only;	/* Manufacturing EEPROM programmed at factory */
 		reg = <0x50>;
@@ -190,6 +211,7 @@ 
 		host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
 		device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
 		clocks = <&osc_32k>;
+		max-speed = <4000000>;
 		clock-names = "extclk";
 	};
 };
@@ -270,9 +292,9 @@ 
 			>;
 		};
 
-		pinctrl_pmic: pmicirq {
+		pinctrl_pmic: pmicirqgrp {
 			fsl,pins = <
-				MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x41
+				MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x141
 			>;
 		};
 
@@ -289,7 +311,7 @@ 
 			>;
 		};
 
-		pinctrl_usdhc1_gpio: usdhc1grpgpio {
+		pinctrl_usdhc1_gpio: usdhc1gpiogrp {
 			fsl,pins = <
 				MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41
 			>;
@@ -306,7 +328,7 @@ 
 			>;
 		};
 
-		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+		pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
 			fsl,pins = <
 				MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
 				MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
@@ -317,7 +339,7 @@ 
 			>;
 		};
 
-		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+		pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
 			fsl,pins = <
 				MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
 				MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
@@ -344,7 +366,7 @@ 
 			>;
 		};
 
-		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+		pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 			fsl,pins = <
 				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
 				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
@@ -360,7 +382,7 @@ 
 			>;
 		};
 
-		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+		pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 			fsl,pins = <
 				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
 				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6