From patchwork Fri Nov 20 15:48:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aswath Govindraju X-Patchwork-Id: 1403855 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=Uel1bCO+; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Cd1Fc4WP2z9sRR for ; Sat, 21 Nov 2020 02:49:40 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9E43282591; Fri, 20 Nov 2020 16:49:35 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="Uel1bCO+"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id A999C825A8; Fri, 20 Nov 2020 16:49:34 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6E920825A2 for ; Fri, 20 Nov 2020 16:49:31 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=a-govindraju@ti.com Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0AKFnUEh123108 for ; Fri, 20 Nov 2020 09:49:30 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1605887370; bh=z7bCO1xXRfucGzaVWC6zqaQtCJEDlAGet8Vs+EitcUQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Uel1bCO+ksdBq1HYDqoEX++TfJPxJIDcdco3D7n1h/LLp1Vu30Sq14ep8bE22MubF //ODpN/b5cUjqwJ9UwVdw17Et7uAMOtnlZdraf0L8354UJ1TzShO0IOMkOYfS5CmDC +C798ZzbPSPRRhBc0prEzj3kTOsH7TuHVONF8B4w= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0AKFnUeG061366 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Fri, 20 Nov 2020 09:49:30 -0600 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 20 Nov 2020 09:49:29 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 20 Nov 2020 09:49:29 -0600 Received: from gsaswath-HP-ProBook-640-G5.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0AKFn6TE074589; Fri, 20 Nov 2020 09:49:23 -0600 From: Aswath Govindraju To: CC: , Dave Gerlach , Grygorii Strashko , Faiz Abbas , Lokesh Vutla , Vignesh Raghavendra , Sekhar Nori , Aswath Govindraju , Roger Quadros Subject: [PATCH 1/3] board: ti: am65x: Set SERDES0 mux to PCIe to use USB 2.0 interface Date: Fri, 20 Nov 2020 21:18:53 +0530 Message-ID: <20201120154855.9065-2-a-govindraju@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201120154855.9065-1-a-govindraju@ti.com> References: <20201120154855.9065-1-a-govindraju@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean It has been observed that setting SERDES0 lane mux to USB prevents USB 2.0 operation on USB0. Setting SERDES0 lane mux to non-USB when USB0 is used in USB 2.0 only mode solves this issue. However, for USB3.0+2.0 operation this issue is not present. Implement this workaround by writing 1 to LANE_FUNC_SEL field in CTRLMMR_SERDES0_CTRL register. Signed-off-by: Aswath Govindraju --- board/ti/am65x/evm.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c index 36063b11383d..4438f14e4ff1 100644 --- a/board/ti/am65x/evm.c +++ b/board/ti/am65x/evm.c @@ -38,6 +38,10 @@ enum { /* Max number of MAC addresses that are parsed/processed per daughter card */ #define DAUGHTER_CARD_NO_OF_MAC_ADDR 8 +/* Regiter that controls the SERDES0 lane and clock assignment */ +#define CTRLMMR_SERDES0_CTRL 0x00104080 +#define PCIE_LANE0 0x1 + DECLARE_GLOBAL_DATA_PTR; int board_init(void) @@ -312,6 +316,18 @@ static int probe_daughtercards(void) (uchar *)mac_addr[j]); } + /* + * It has been observed that setting SERDES0 lane mux to USB prevents USB + * 2.0 operation on USB0. Setting SERDES0 lane mux to non-USB when USB0 is + * used in USB 2.0 only mode solves this issue. For USB3.0+2.0 operation + * this issue is not present. + * + * Implement this workaround by writing 1 to LANE_FUNC_SEL field in + * CTRLMMR_SERDES0_CTRL register. + */ + if (!strncmp(ep.name, "SER-PCIE2LEVM", sizeof(ep.name))) + writel(PCIE_LANE0, CTRLMMR_SERDES0_CTRL); + /* Skip if no overlays are to be added */ if (!strlen(cards[i].dtbo_name)) continue;