@@ -19,7 +19,7 @@
};
aliases {
- spi0 = &snfi;
+ spi0 = &snor;
};
memory@40000000 {
@@ -151,6 +151,18 @@
quad-spi;
};
+&snor {
+ pinctrl-names = "default";
+ pinctrl-0 = <&snor_pins>;
+ status = "okay";
+
+ spi-flash@0{
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
@@ -68,7 +68,14 @@
assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
<&topckgen CLK_TOP_UNIVPLL2_D8>;
+ };
+ snor: snor@11014000 {
+ compatible = "mediatek,mtk-snor";
+ reg = <0x11014000 0x1000>;
+ clocks = <&pericfg CLK_PERI_FLASH_PD>,
+ <&topckgen CLK_TOP_FLASH_SEL>;
+ clock-names = "spi", "sf";
status = "disabled";
};
@@ -14,7 +14,7 @@
compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
aliases {
- spi0 = &snfi;
+ spi0 = &snor;
};
chosen {
@@ -76,6 +76,18 @@
};
};
+&snor {
+ pinctrl-names = "default";
+ pinctrl-0 = <&snor_pins>;
+ status = "okay";
+
+ spi-flash@0{
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
@@ -222,6 +222,15 @@
#size-cells = <0>;
};
+ snor: snor@11014000 {
+ compatible = "mediatek,mtk-snor";
+ reg = <0x11014000 0x1000>;
+ clocks = <&pericfg CLK_PERI_FLASH_PD>,
+ <&topckgen CLK_TOP_FLASH_SEL>;
+ clock-names = "spi", "sf";
+ status = "disabled";
+ };
+
ethsys: syscon@1b000000 {
compatible = "mediatek,mt7629-ethsys", "syscon";
reg = <0x1b000000 0x1000>;
@@ -54,7 +54,8 @@ CONFIG_DM_SERIAL=y
CONFIG_MTK_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
-CONFIG_MTK_SNFI_SPI=y
+# CONFIG_MTK_SNFI_SPI is not set
+CONFIG_MTK_SNOR=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_TIMER=y
CONFIG_MTK_TIMER=y
@@ -65,7 +65,8 @@ CONFIG_DM_SERIAL=y
CONFIG_MTK_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
-CONFIG_MTK_SNFI_SPI=y
+# CONFIG_MTK_SNFI_SPI is not set
+CONFIG_MTK_SNOR=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y