diff mbox series

[RESEND,v2,22/22] arm: socfpga: dm: Enable Intel Diamond Mesa build

Message ID 20201110064439.9683-23-elly.siew.chin.lim@intel.com
State New
Delegated to: Simon Goldschmidt
Headers show
Series Add Intel Diamond Mesa SoC support | expand

Commit Message

Lim, Elly Siew Chin Nov. 10, 2020, 6:44 a.m. UTC
Add defconfig for Diamond Mesa to support both
legacy boot flow and ATF boot flow.

Legacy boot:
SPL -> U-Boot proper -> OS (Linux)

ATF boot flow:
SPL -> ATF(BL31) -> U-Boot proper -> OS (Linux)

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
---
 arch/arm/mach-socfpga/Kconfig    | 19 ++++++++++
 arch/arm/mach-socfpga/Makefile   | 18 ++++++++++
 configs/socfpga_dm_atf_defconfig | 76 ++++++++++++++++++++++++++++++++++++++++
 configs/socfpga_dm_defconfig     | 69 ++++++++++++++++++++++++++++++++++++
 4 files changed, 182 insertions(+)
 create mode 100644 configs/socfpga_dm_atf_defconfig
 create mode 100644 configs/socfpga_dm_defconfig

Comments

Tan, Ley Foon Nov. 23, 2020, 10:57 a.m. UTC | #1
> -----Original Message-----
> From: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> Sent: Tuesday, November 10, 2020 2:45 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Tan, Ley Foon
> <ley.foon.tan@intel.com>; See, Chin Liang <chin.liang.see@intel.com>;
> Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@intel.com>; Westergreen, Dalon
> <dalon.westergreen@intel.com>; Simon Glass <sjg@chromium.org>; Gan,
> Yau Wai <yau.wai.gan@intel.com>; Lim, Elly Siew Chin
> <elly.siew.chin.lim@intel.com>
> Subject: [RESEND v2 22/22] arm: socfpga: dm: Enable Intel Diamond Mesa
> build
> 
> Add defconfig for Diamond Mesa to support both legacy boot flow and ATF
> boot flow.
> 
> Legacy boot:
> SPL -> U-Boot proper -> OS (Linux)
> 
> ATF boot flow:
> SPL -> ATF(BL31) -> U-Boot proper -> OS (Linux)
> 
> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
> ---
>  arch/arm/mach-socfpga/Kconfig    | 19 ++++++++++
>  arch/arm/mach-socfpga/Makefile   | 18 ++++++++++
>  configs/socfpga_dm_atf_defconfig | 76
> ++++++++++++++++++++++++++++++++++++++++
>  configs/socfpga_dm_defconfig     | 69
> ++++++++++++++++++++++++++++++++++++
>  4 files changed, 182 insertions(+)
>  create mode 100644 configs/socfpga_dm_atf_defconfig  create mode
> 100644 configs/socfpga_dm_defconfig
> 
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-
> socfpga/Kconfig index 4d061a9d0d..5dee193b31 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -66,6 +66,22 @@ config TARGET_SOCFPGA_CYCLONE5
>  	bool
>  	select TARGET_SOCFPGA_GEN5
> 
> +config TARGET_SOCFPGA_DM
> +	bool
> +	select TARGET_SOCFPGA_SOC64
> +	select ARMV8_MULTIENTRY
> +	select ARMV8_SET_SMPEN
> +	select CLK
> +	select FPGA_INTEL_SDM_MAILBOX
> +	select NCORE_CACHE
> +	select SPL_ALTERA_SDRAM
> +	select SPL_CLK if SPL
> +	select BINMAN
Sort in alphanumerical order.


Regards
Ley Foon
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 4d061a9d0d..5dee193b31 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -66,6 +66,22 @@  config TARGET_SOCFPGA_CYCLONE5
 	bool
 	select TARGET_SOCFPGA_GEN5
 
+config TARGET_SOCFPGA_DM
+	bool
+	select TARGET_SOCFPGA_SOC64
+	select ARMV8_MULTIENTRY
+	select ARMV8_SET_SMPEN
+	select CLK
+	select FPGA_INTEL_SDM_MAILBOX
+	select NCORE_CACHE
+	select SPL_ALTERA_SDRAM
+	select SPL_CLK if SPL
+	select BINMAN
+
+config TARGET_SOCFPGA_DM_SOCDK
+	bool "Intel SOCFPGA SoCDK (Diamond Mesa)"
+	select TARGET_SOCFPGA_DM
+
 config TARGET_SOCFPGA_GEN5
 	bool
 	select SPL_ALTERA_SDRAM
@@ -165,6 +181,7 @@  config SYS_BOARD
 	default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
+	default "dm-socdk" if TARGET_SOCFPGA_DM_SOCDK
 	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 	default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
@@ -179,6 +196,7 @@  config SYS_BOARD
 
 config SYS_VENDOR
 	default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
+	default "intel" if TARGET_SOCFPGA_DM_SOCDK
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
 	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -203,6 +221,7 @@  config SYS_CONFIG_NAME
 	default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
+	default "socfpga_dm_socdk" if TARGET_SOCFPGA_DM_SOCDK
 	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 	default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 57dc1e730d..b88bb515d0 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -54,6 +54,19 @@  obj-y	+= wrap_handoff_soc64.o
 obj-y	+= wrap_pll_config_soc64.o
 endif
 
+ifdef CONFIG_TARGET_SOCFPGA_DM
+obj-y	+= clock_manager_dm.o
+obj-y	+= lowlevel_init_soc64.o
+obj-y	+= mailbox_s10.o
+obj-y	+= misc_s10.o
+obj-y	+= mmu-arm64_s10.o
+obj-y	+= reset_manager_s10.o
+obj-y	+= system_manager_soc64.o
+obj-y	+= timer_s10.o
+obj-y	+= wrap_handoff_soc64.o
+obj-y	+= wrap_pll_config_soc64.o
+endif
+
 ifdef CONFIG_SPL_BUILD
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
 obj-y	+= spl_gen5.o
@@ -75,6 +88,11 @@  obj-y	+= firewall.o
 obj-y	+= spl_agilex.o
 obj-y	+= spl_soc64.o
 endif
+ifdef CONFIG_TARGET_SOCFPGA_DM
+obj-y	+= firewall.o
+obj-y	+= spl_dm.o
+obj-y	+= spl_soc64.o
+endif
 else
 obj-$(CONFIG_SPL_ATF) += smc_api.o
 endif
diff --git a/configs/socfpga_dm_atf_defconfig b/configs/socfpga_dm_atf_defconfig
new file mode 100644
index 0000000000..975f20c752
--- /dev/null
+++ b/configs/socfpga_dm_atf_defconfig
@@ -0,0 +1,76 @@ 
+CONFIG_ARM=y
+CONFIG_ARM_SMCCC=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_TEXT_BASE=0x200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x200
+CONFIG_DM_GPIO=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_SOCFPGA_DM_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_dm"
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_BOOTDELAY=5
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="earlycon"
+CONFIG_SPL_CACHE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="SOCFPGA_DM # "
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_GPIO is not set
+# CONFIG_CMD_I2C is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_MTD is not set
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_USB is not set
+# CONFIG_CMD_DHCP is not set
+# CONFIG_CMD_MII is not set
+# CONFIG_CMD_PING is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_dm_socdk"
+CONFIG_ENV_IS_NOWHERE=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+# CONFIG_DWAPB_GPIO is not set
+# CONFIG_DM_I2C is not set
+# CONFIG_SYS_I2C_DW is not set
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_MTD=y
+CONFIG_SF_DEFAULT_MODE=0x2003
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
+CONFIG_DM_RESET=y
+CONFIG_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+CONFIG_DESIGNWARE_WATCHDOG=y
+CONFIG_WDT=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_PANIC_HANG=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_BAUDRATE=4800
diff --git a/configs/socfpga_dm_defconfig b/configs/socfpga_dm_defconfig
new file mode 100644
index 0000000000..d87f849c42
--- /dev/null
+++ b/configs/socfpga_dm_defconfig
@@ -0,0 +1,69 @@ 
+CONFIG_ARM=y
+CONFIG_ARM_SMCCC=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_TEXT_BASE=0x1000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x200
+CONFIG_DM_GPIO=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_SOCFPGA_DM_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_dm"
+CONFIG_SPL_FS_FAT=y
+# CONFIG_PSCI_RESET is not set
+CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_BOOTDELAY=5
+CONFIG_SPL_CACHE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="SOCFPGA_DM # "
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_GPIO is not set
+# CONFIG_CMD_I2C is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_MTD is not set
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_USB is not set
+# CONFIG_CMD_DHCP is not set
+# CONFIG_CMD_MII is not set
+# CONFIG_CMD_PING is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_dm_socdk"
+CONFIG_ENV_IS_NOWHERE=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+# CONFIG_DWAPB_GPIO is not set
+# CONFIG_DM_I2C is not set
+# CONFIG_SYS_I2C_DW is not set
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_MTD=y
+CONFIG_SF_DEFAULT_MODE=0x2003
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
+CONFIG_DM_RESET=y
+CONFIG_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+CONFIG_DESIGNWARE_WATCHDOG=y
+CONFIG_WDT=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_PANIC_HANG=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_BAUDRATE=4800