diff mbox series

[RESEND,v2,15/22] arm: socfpga: dm: Add clock manager for Diamond Mesa

Message ID 20201110064439.9683-16-elly.siew.chin.lim@intel.com
State New
Delegated to: Simon Goldschmidt
Headers show
Series Add Intel Diamond Mesa SoC support | expand

Commit Message

Lim, Elly Siew Chin Nov. 10, 2020, 6:44 a.m. UTC
Add clock manager for Diamond Mesa.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
---
 arch/arm/mach-socfpga/clock_manager_dm.c           | 79 ++++++++++++++++++++++
 arch/arm/mach-socfpga/include/mach/clock_manager.h |  2 +
 .../mach-socfpga/include/mach/clock_manager_dm.h   | 14 ++++
 3 files changed, 95 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_dm.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_dm.h

Comments

Tan, Ley Foon Nov. 23, 2020, 8:45 a.m. UTC | #1
> -----Original Message-----
> From: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> Sent: Tuesday, November 10, 2020 2:45 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Tan, Ley Foon
> <ley.foon.tan@intel.com>; See, Chin Liang <chin.liang.see@intel.com>;
> Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@intel.com>; Westergreen, Dalon
> <dalon.westergreen@intel.com>; Simon Glass <sjg@chromium.org>; Gan,
> Yau Wai <yau.wai.gan@intel.com>; Lim, Elly Siew Chin
> <elly.siew.chin.lim@intel.com>
> Subject: [RESEND v2 15/22] arm: socfpga: dm: Add clock manager for
> Diamond Mesa
> 
> Add clock manager for Diamond Mesa.
> 
> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
> ---
>  arch/arm/mach-socfpga/clock_manager_dm.c           | 79
> ++++++++++++++++++++++
>  arch/arm/mach-socfpga/include/mach/clock_manager.h |  2 +
>  .../mach-socfpga/include/mach/clock_manager_dm.h   | 14 ++++
>  3 files changed, 95 insertions(+)
>  create mode 100644 arch/arm/mach-socfpga/clock_manager_dm.c
>  create mode 100644 arch/arm/mach-
> socfpga/include/mach/clock_manager_dm.h
> 
> diff --git a/arch/arm/mach-socfpga/clock_manager_dm.c
> b/arch/arm/mach-socfpga/clock_manager_dm.c
> new file mode 100644
> index 0000000000..cdf096cd8b
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/clock_manager_dm.c
> @@ -0,0 +1,79 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Intel Corporation <www.intel.com>
> + *
> + */
> +
> +#include <clk.h>
> +#include <common.h>
> +#include <dm.h>
> +#include <malloc.h>
> +#include <asm/arch/clock_manager.h>
> +#include <asm/arch/system_manager.h>
> +#include <asm/io.h>
> +#include <dt-bindings/clock/dm-clock.h>
Try to sort alphanumerical order.


[...]

> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> index 0f0cb230fa..a164f47bda 100644
> --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> @@ -26,6 +26,8 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>  #include <asm/arch/clock_manager_s10.h>  #elif
> defined(CONFIG_TARGET_SOCFPGA_AGILEX)
>  #include <asm/arch/clock_manager_agilex.h>
> +#elif defined(CONFIG_TARGET_SOCFPGA_DM) #include
> +<asm/arch/clock_manager_dm.h>
>  #endif
> 
>  #endif /* _CLOCK_MANAGER_H_ */
> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h
> b/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h
> new file mode 100644
> index 0000000000..a355fda692
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2020 Intel Corporation <www.intel.com>  */
> +
> +#ifndef _CLOCK_MANAGER_DM_
> +#define _CLOCK_MANAGER_DM_
> +
> +unsigned long cm_get_mpu_clk_hz(void);
This can move to clock_manager.h, since all devices have this.


Regards
Ley Foon
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/clock_manager_dm.c b/arch/arm/mach-socfpga/clock_manager_dm.c
new file mode 100644
index 0000000000..cdf096cd8b
--- /dev/null
+++ b/arch/arm/mach-socfpga/clock_manager_dm.c
@@ -0,0 +1,79 @@ 
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/dm-clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong cm_get_rate_dm(u32 id)
+{
+	struct udevice *dev;
+	struct clk clk;
+	ulong rate;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_CLK,
+					  DM_GET_DRIVER(socfpga_dm_clk),
+					  &dev);
+	if (ret)
+		return 0;
+
+	clk.id = id;
+	ret = clk_request(dev, &clk);
+	if (ret < 0)
+		return 0;
+
+	rate = clk_get_rate(&clk);
+
+	clk_free(&clk);
+
+	if ((rate == (unsigned long)-ENXIO) ||
+	    (rate == (unsigned long)-EIO)) {
+		debug("%s id %u: clk_get_rate err: %ld\n",
+		      __func__, id, rate);
+		return 0;
+	}
+
+	return rate;
+}
+
+static u32 cm_get_rate_dm_khz(u32 id)
+{
+	return cm_get_rate_dm(id) / 1000;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+	return cm_get_rate_dm(DM_MPU_CLK);
+}
+
+unsigned int cm_get_l4_sys_free_clk_hz(void)
+{
+	return cm_get_rate_dm(DM_L4_SYS_FREE_CLK);
+}
+
+void cm_print_clock_quick_summary(void)
+{
+	printf("MPU       %10d kHz\n",
+	       cm_get_rate_dm_khz(DM_MPU_CLK));
+	printf("L4 Main	    %8d kHz\n",
+	       cm_get_rate_dm_khz(DM_L4_MAIN_CLK));
+	printf("L4 sys free %8d kHz\n",
+	       cm_get_rate_dm_khz(DM_L4_SYS_FREE_CLK));
+	printf("L4 MP       %8d kHz\n",
+	       cm_get_rate_dm_khz(DM_L4_MP_CLK));
+	printf("L4 SP       %8d kHz\n",
+	       cm_get_rate_dm_khz(DM_L4_SP_CLK));
+	printf("SDMMC       %8d kHz\n",
+	       cm_get_rate_dm_khz(DM_SDMMC_CLK));
+}
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 0f0cb230fa..a164f47bda 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -26,6 +26,8 @@  unsigned int cm_get_qspi_controller_clk_hz(void);
 #include <asm/arch/clock_manager_s10.h>
 #elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
 #include <asm/arch/clock_manager_agilex.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_DM)
+#include <asm/arch/clock_manager_dm.h>
 #endif
 
 #endif /* _CLOCK_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h b/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h
new file mode 100644
index 0000000000..a355fda692
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h
@@ -0,0 +1,14 @@ 
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _CLOCK_MANAGER_DM_
+#define _CLOCK_MANAGER_DM_
+
+unsigned long cm_get_mpu_clk_hz(void);
+
+#include <asm/arch/clock_manager_soc64.h>
+#include "../../../../../drivers/clk/altera/clk-dm.h"
+
+#endif /* _CLOCK_MANAGER_DM_ */