From patchwork Wed Oct 28 09:49:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick DELAUNAY X-Patchwork-Id: 1389194 X-Patchwork-Delegate: patrick.delaunay73@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=st.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=st.com header.i=@st.com header.a=rsa-sha256 header.s=STMicroelectronics header.b=o86/J4ut; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CLkLg532Jz9sVW for ; Wed, 28 Oct 2020 20:49:31 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 21EDC823F4; Wed, 28 Oct 2020 10:49:18 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=st.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=st.com header.i=@st.com header.b="o86/J4ut"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 24F0E801D8; Wed, 28 Oct 2020 10:49:17 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 49DFC801D8 for ; Wed, 28 Oct 2020 10:49:13 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=st.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=patrick.delaunay@st.com Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 09S9kvRj006065; Wed, 28 Oct 2020 10:49:12 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=STMicroelectronics; bh=lw5eqcIgvxNAa2njJoK1lodZQn5rB5jwJSp+pwz0w4c=; b=o86/J4utkHrA9Ar7saL1C4tHv61QWaaaoV9uve91M0m78Cg2EWD+Rzb7y0LkY6UaAEfF SL1COcZj/oSnKtkRukBhvE44AyNzKTBPmgucmZiuYBoGkl3hdSrKchj7xvTXxM/gc0Ym iVIRqJIkV+aNMYQPeVgwU+HpszOy8wKoSis6UvDjzgscqPa4B6hHe0yo26r6fWCP5uay 9PmnYkkhbpM/3u61ii3QGQTTyLIhO6lvmh6KpAV5WXcVeknrz1oANaF5MR2O8LboWlsl kq5PWufyD55BtdMYMnA0NvOJH78AQazdWmQDzyKHT+oJSFfPViXVGxeExNMNZnbpgqgm Sg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 34ccj20a7b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 28 Oct 2020 10:49:12 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 8068D10003A; Wed, 28 Oct 2020 10:49:11 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node3.st.com [10.75.127.6]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 611002A4D60; Wed, 28 Oct 2020 10:49:11 +0100 (CET) Received: from localhost (10.75.127.48) by SFHDAG2NODE3.st.com (10.75.127.6) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 28 Oct 2020 10:49:10 +0100 From: Patrick Delaunay To: CC: Patrick Delaunay , Patrice Chotard , U-Boot STM32 Subject: [PATCH 1/2] pinctrl: stm32: display bias information for all pins Date: Wed, 28 Oct 2020 10:49:07 +0100 Message-ID: <20201028094908.11031-1-patrick.delaunay@st.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.75.127.48] X-ClientProxiedBy: SFHDAG3NODE2.st.com (10.75.127.8) To SFHDAG2NODE3.st.com (10.75.127.6) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-10-28_04:2020-10-26, 2020-10-28 signatures=0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Display the bias information for input gpios or AF configuration, and not only for output pin, as described in Reference manual (Table 81. Port bit configuration table). Fixes: da7a0bb1f279 ("pinctrl: stm32: add information on pin configuration") Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/pinctrl/pinctrl_stm32.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index dbea99532c..262b2c3d7e 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -48,15 +48,15 @@ static const char * const pinmux_mode[PINMUX_MODE_COUNT] = { "alt function", }; -static const char * const pinmux_output[] = { - [STM32_GPIO_PUPD_NO] = "bias-disable", - [STM32_GPIO_PUPD_UP] = "bias-pull-up", - [STM32_GPIO_PUPD_DOWN] = "bias-pull-down", +static const char * const pinmux_bias[] = { + [STM32_GPIO_PUPD_NO] = "", + [STM32_GPIO_PUPD_UP] = "pull-up", + [STM32_GPIO_PUPD_DOWN] = "pull-down", }; static const char * const pinmux_input[] = { - [STM32_GPIO_OTYPE_PP] = "drive-push-pull", - [STM32_GPIO_OTYPE_OD] = "drive-open-drain", + [STM32_GPIO_OTYPE_PP] = "push-pull", + [STM32_GPIO_OTYPE_OD] = "open-drain", }; static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset) @@ -213,6 +213,7 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev, dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n", selector, gpio_idx, mode); priv = dev_get_priv(gpio_dev); + pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & PUPD_MASK; switch (mode) { @@ -224,20 +225,19 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev, break; case GPIOF_FUNC: af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx); - snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num); + snprintf(buf, size, "%s %d %s", pinmux_mode[mode], af_num, + pinmux_bias[pupd]); break; case GPIOF_OUTPUT: - pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & - PUPD_MASK; snprintf(buf, size, "%s %s %s", - pinmux_mode[mode], pinmux_output[pupd], + pinmux_mode[mode], pinmux_bias[pupd], label ? label : ""); break; case GPIOF_INPUT: otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK; - snprintf(buf, size, "%s %s %s", + snprintf(buf, size, "%s %s %s %s", pinmux_mode[mode], pinmux_input[otype], - label ? label : ""); + pinmux_bias[pupd], label ? label : ""); break; }