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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id 12sm3117558ioz.33.2020.10.16.15.58.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Oct 2020 15:58:23 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de, uboot-snps-arc@synopsys.com Cc: Jagan Teki , Marek Vasut , Heinrich Schuchardt , Eugeniy Paltsev , Horatiu Vultur , Sean Anderson Subject: [PATCH v4 05/13] spi: dw: Rename registers to match datasheet Date: Fri, 16 Oct 2020 18:57:47 -0400 Message-Id: <20201016225755.302659-6-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201016225755.302659-1-seanga2@gmail.com> References: <20201016225755.302659-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean A few registers had slightly different names from what is in the datasheet. Signed-off-by: Sean Anderson --- (no changes since v1) drivers/spi/designware_spi.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index e8ba80ef41..8abcdde8a3 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -27,14 +27,14 @@ #include /* Register offsets */ -#define DW_SPI_CTRL0 0x00 -#define DW_SPI_CTRL1 0x04 +#define DW_SPI_CTRLR0 0x00 +#define DW_SPI_CTRLR1 0x04 #define DW_SPI_SSIENR 0x08 #define DW_SPI_MWCR 0x0c #define DW_SPI_SER 0x10 #define DW_SPI_BAUDR 0x14 -#define DW_SPI_TXFLTR 0x18 -#define DW_SPI_RXFLTR 0x1c +#define DW_SPI_TXFTLR 0x18 +#define DW_SPI_RXFTLR 0x1c #define DW_SPI_TXFLR 0x20 #define DW_SPI_RXFLR 0x24 #define DW_SPI_SR 0x28 @@ -191,13 +191,13 @@ static void spi_hw_init(struct udevice *bus, struct dw_spi_priv *priv) u32 fifo; for (fifo = 1; fifo < 256; fifo++) { - dw_write(priv, DW_SPI_TXFLTR, fifo); - if (fifo != dw_read(priv, DW_SPI_TXFLTR)) + dw_write(priv, DW_SPI_TXFTLR, fifo); + if (fifo != dw_read(priv, DW_SPI_TXFTLR)) break; } priv->fifo_len = (fifo == 1) ? 0 : fifo; - dw_write(priv, DW_SPI_TXFLTR, 0); + dw_write(priv, DW_SPI_TXFTLR, 0); } dev_dbg(bus, "fifo_len=%d\n", priv->fifo_len); } @@ -443,8 +443,8 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen, dev_dbg(dev, "cr0=%08x rx=%p tx=%p len=%d [bytes]\n", cr0, rx, tx, priv->len); /* Reprogram cr0 only if changed */ - if (dw_read(priv, DW_SPI_CTRL0) != cr0) - dw_write(priv, DW_SPI_CTRL0, cr0); + if (dw_read(priv, DW_SPI_CTRLR0) != cr0) + dw_write(priv, DW_SPI_CTRLR0, cr0); /* * Configure the desired SS (slave select 0...3) in the controller