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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id d9sm6170597qtg.51.2020.10.04.13.29.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Oct 2020 13:29:57 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Bin Meng , Simon Glass , Pragnesh Patel , Rick Chen , Sean Anderson Subject: [PATCH 1/3] riscv: Move Andes PLMT driver to drivers/timer Date: Sun, 4 Oct 2020 16:29:45 -0400 Message-Id: <20201004202947.469166-2-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201004202947.469166-1-seanga2@gmail.com> References: <20201004202947.469166-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass Reviewed-by: Rick Chen --- MAINTAINERS | 1 + arch/riscv/Kconfig | 7 ------- arch/riscv/lib/Makefile | 1 - drivers/timer/Kconfig | 7 +++++++ drivers/timer/Makefile | 1 + .../lib/andes_plmt.c => drivers/timer/andes_plmt_timer.c | 0 6 files changed, 9 insertions(+), 8 deletions(-) rename arch/riscv/lib/andes_plmt.c => drivers/timer/andes_plmt_timer.c (100%) diff --git a/MAINTAINERS b/MAINTAINERS index c96b8b6baa..32a2cdb52b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -927,6 +927,7 @@ S: Maintained T: git https://gitlab.denx.de/u-boot/custodians/u-boot-riscv.git F: arch/riscv/ F: cmd/riscv/ +F: drivers/timer/andes_plmt_timer.c F: tools/prelink-riscv.c RISC-V KENDRYTE diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index aaa3b833a5..30934d9cc6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -170,13 +170,6 @@ config ANDES_PLIC The Andes PLIC block holds memory-mapped claim and pending registers associated with software interrupt. -config ANDES_PLMT - bool - depends on RISCV_MMODE || SPL_RISCV_MMODE - help - The Andes PLMT block holds memory-mapped mtime register - associated with timer tick. - config SYS_MALLOC_F_LEN default 0x1000 diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 10ac5b06d3..12c14f2019 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -13,7 +13,6 @@ obj-y += cache.o ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y) obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o obj-$(CONFIG_ANDES_PLIC) += andes_plic.o -obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o else obj-$(CONFIG_SBI) += sbi.o obj-$(CONFIG_SBI_IPI) += sbi_ipi.o diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index d40d313011..2f9c8f84f0 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -53,6 +53,13 @@ config ALTERA_TIMER Select this to enable a timer for Altera devices. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config ANDES_PLMT + bool + depends on RISCV_MMODE || SPL_RISCV_MMODE + help + The Andes PLMT block holds memory-mapped mtime register + associated with timer tick. + config ARC_TIMER bool "ARC timer support" depends on TIMER && ARC && CLK diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index c22ffebcde..d22813127f 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -5,6 +5,7 @@ obj-y += timer-uclass.o obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o +obj-$(CONFIG_ANDES_PLMT) += andes_plmt_timer.o obj-$(CONFIG_ARC_TIMER) += arc_timer.o obj-$(CONFIG_AST_TIMER) += ast_timer.o obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o diff --git a/arch/riscv/lib/andes_plmt.c b/drivers/timer/andes_plmt_timer.c similarity index 100% rename from arch/riscv/lib/andes_plmt.c rename to drivers/timer/andes_plmt_timer.c