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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id l6sm117535qkb.56.2020.09.29.07.18.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2020 07:18:54 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Bin Meng , Rick Chen , Heinrich Schuchardt , Sean Anderson Subject: [PATCH 08/10] riscv: Probe ram in dram_init Date: Tue, 29 Sep 2020 10:18:33 -0400 Message-Id: <20200929141835.38435-9-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200929141835.38435-1-seanga2@gmail.com> References: <20200929141835.38435-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean If CONFIG_RAM is enabled, use the ram device to get the base/size of memory. This provides an easy way for boards/cpus to hook into the dram_init logic, without needing to provide a second SYS_CPU. Signed-off-by: Sean Anderson --- arch/riscv/cpu/generic/dram.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c index 1dc77efeca..fbcd4ddf5f 100644 --- a/arch/riscv/cpu/generic/dram.c +++ b/arch/riscv/cpu/generic/dram.c @@ -4,15 +4,41 @@ */ #include +#include #include #include +#include +#include #include DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { +#if CONFIG_IS_ENABLED(RAM) + int ret; + struct ram_info info; + struct udevice *dev; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return ret; + } + + ret = ram_get_info(dev, &info); + if (ret) { + debug("Cannot get DRAM size: %d\n", ret); + return ret; + } + + gd->ram_base = info.base; + gd->ram_size = info.size; + + return 0; +#else return fdtdec_setup_mem_size_base(); +#endif } int dram_init_banksize(void)