diff mbox series

[01/10] clk: k210: Fix PLLs not being enabled

Message ID 20200929141835.38435-2-seanga2@gmail.com
State Superseded
Delegated to: Andes
Headers show
Series riscv: k210: Enable use of AI ram bank | expand

Commit Message

Sean Anderson Sept. 29, 2020, 2:18 p.m. UTC 
After starting or setting the rate of a PLL, the enable bit must be set.

This fixes a bug where the AI ram would not be accessible, because it
requires PLL1 to be running.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

 drivers/clk/kendryte/pll.c | 2 ++
 1 file changed, 2 insertions(+)
diff mbox series

Patch

diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c
index ab6d75d585..f198920113 100644
--- a/drivers/clk/kendryte/pll.c
+++ b/drivers/clk/kendryte/pll.c
@@ -531,6 +531,7 @@  static int k210_pll_enable(struct clk *clk)
 	k210_pll_waitfor_lock(pll);
 
 	reg &= ~K210_PLL_BYPASS;
+	reg |= K210_PLL_EN;
 	writel(reg, pll->reg);
 
 	return 0;
@@ -550,6 +551,7 @@  static int k210_pll_disable(struct clk *clk)
 	writel(reg, pll->reg);
 
 	reg &= ~K210_PLL_PWRD;
+	reg &= ~K210_PLL_EN;
 	writel(reg, pll->reg);
 	return 0;
 }