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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id c70sm8658105qkg.4.2020.09.21.04.51.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2020 04:51:56 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Heinrich Schuchardt , Rick Chen , alankao@andestech.com, Leo Liang , Bin Meng , Sean Anderson , Bin Meng , Rick Chen Subject: [PATCH v3 2/7] riscv: Match memory barriers between send_ipi_many and handle_ipi Date: Mon, 21 Sep 2020 07:51:36 -0400 Message-Id: <20200921115141.70598-3-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200921115141.70598-1-seanga2@gmail.com> References: <20200921115141.70598-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Without a matching barrier on the write side, the barrier in handle_ipi does nothing. It was entirely possible for the boot hart to write to addr, arg0, and arg1 *after* sending the IPI, because there was no barrier on the sending side. Fixes: 90ae281437 ("riscv: add option to wait for ack from secondary harts in smp functions") Signed-off-by: Sean Anderson Reviewed-by: Bin Meng Reviewed-by: Rick Chen Reviewed-by: Leo Liang --- (no changes since v1) arch/riscv/lib/smp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index ac22136314..ab6d8bd7fa 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -54,6 +54,8 @@ static int send_ipi_many(struct ipi_data *ipi, int wait) gd->arch.ipi[reg].arg0 = ipi->arg0; gd->arch.ipi[reg].arg1 = ipi->arg1; + __smp_mb(); + ret = riscv_send_ipi(reg); if (ret) { pr_err("Cannot send IPI to hart %d\n", reg);