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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id k20sm14770988qtb.34.2020.09.14.07.23.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2020 07:23:16 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: alankao@andestech.com, Leo Liang , Heinrich Schuchardt , Bin Meng , Rick Chen , Sean Anderson Subject: [PATCH v2 1/7] Revert "riscv: Clear pending interrupts before enabling IPIs" Date: Mon, 14 Sep 2020 10:22:57 -0400 Message-Id: <20200914142303.21307-2-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200914142303.21307-1-seanga2@gmail.com> References: <20200914142303.21307-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Clearing MIP.MSIP is not guaranteed to do anything by the spec. In addition, most existing RISC-V hardware does nothing when this bit is set. The following commits "riscv: Use a valid bit to ignore already-pending IPIs" and "riscv: Clear pending IPIs on initialization" should implement the original intent of the reverted commit in a more robust manner. This reverts commit 9472630337e7c4ac442066b5a752aaa8c3b4d4a6. Signed-off-by: Sean Anderson Reviewed-by: Bin Meng --- I know there is still some discussion in the last series on whether to include this commit, but I'd like to put out another revision and get feedback. (no changes since v1) arch/riscv/cpu/start.S | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index bf9fdf369b..e3222b1ea7 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -65,8 +65,6 @@ _start: #else li t0, SIE_SSIE #endif - /* Clear any pending IPIs */ - csrc MODE_PREFIX(ip), t0 csrs MODE_PREFIX(ie), t0 #endif