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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id s30sm4342831qth.65.2020.09.09.13.09.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2020 13:09:53 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Anup Patel , Pragnesh Patel , Bin Meng , Rick Chen , Sean Anderson , Pragnesh Patel Subject: [PATCH v4 8/8] riscv: Update SiFive device tree for new CLINT driver Date: Wed, 9 Sep 2020 16:09:30 -0400 Message-Id: <20200909200930.232174-9-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200909200930.232174-1-seanga2@gmail.com> References: <20200909200930.232174-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean We currently do this in a u-boot specific dts, but hopefully we can get these bindings added in Linux in the future. Signed-off-by: Sean Anderson Reviewed-by: Pragnesh Patel Reviewed-by: Bin Meng --- This patch builds but has NOT been tested. Changes in v4: - Both the Andes PMLT and Sifive CLINT now fall back on timebase-frequency, per discussion with Anup Patel - Rebase Changes in v3: - Rebase Changes in v2: - Fix SiFive CLINT not getting tick-rate from rtcclk arch/riscv/dts/fu540-c000-u-boot.dtsi | 8 ++++++-- arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 4 ++++ 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi index 5302677ee4..a06e1b11c6 100644 --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -55,9 +55,13 @@ reg = <0x0 0x10070000 0x0 0x1000>; fuse-count = <0x1000>; }; - clint@2000000 { + clint: clint@2000000 { compatible = "riscv,clint0"; - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7 &cpu2_intc 3 &cpu2_intc 7 &cpu3_intc 3 &cpu3_intc 7 &cpu4_intc 3 &cpu4_intc 7>; + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7 + &cpu2_intc 3 &cpu2_intc 7 + &cpu3_intc 3 &cpu3_intc 7 + &cpu4_intc 3 &cpu4_intc 7>; reg = <0x0 0x2000000 0x0 0xc0000>; u-boot,dm-spl; }; diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi index 5d0c928b29..1996149c95 100644 --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi @@ -34,6 +34,10 @@ }; +&clint { + clocks = <&rtcclk>; +}; + &qspi0 { u-boot,dm-spl;