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[73.14.175.90]) by smtp.gmail.com with ESMTPSA id w13sm6232663iox.10.2020.09.06.14.44.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Sep 2020 14:44:52 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Wolfgang Wallner , Bin Meng , Bernhard Messerklinger , Andy Shevchenko , Simon Glass Subject: [PATCH v3 41/57] x86: cpu: Report address width from cpu_get_info() Date: Sun, 6 Sep 2020 15:43:49 -0600 Message-Id: <20200906154340.v3.41.I118f06c4ecc36bca1be6229e54e03511110a84a0@changeid> X-Mailer: git-send-email 2.28.0.526.ge36021eeef-goog In-Reply-To: <20200906214405.71632-1-sjg@chromium.org> References: <20200906214405.71632-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Add support for this new field in the common code used by most x86 CPU drivers. Signed-off-by: Simon Glass --- (no changes since v1) arch/x86/cpu/i386/cpu.c | 23 +++++++++++++++++++++++ arch/x86/cpu/intel_common/cpu.c | 1 + arch/x86/cpu/x86_64/cpu.c | 5 +++++ arch/x86/include/asm/cpu.h | 9 +++++++++ 4 files changed, 38 insertions(+) diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 8f342dd06e2..7517b756f43 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -34,6 +34,10 @@ DECLARE_GLOBAL_DATA_PTR; +#define CPUID_FEATURE_PAE BIT(6) +#define CPUID_FEATURE_PSE36 BIT(17) +#define CPUID_FEAURE_HTT BIT(28) + /* * Constructor for a conventional segment GDT (or LDT) entry * This is a macro so it can be used in initialisers @@ -388,6 +392,25 @@ static void setup_identity(void) } } +static uint cpu_cpuid_extended_level(void) +{ + return cpuid_eax(0x80000000); +} + +int cpu_phys_address_size(void) +{ + if (!has_cpuid()) + return 32; + + if (cpu_cpuid_extended_level() >= 0x80000008) + return cpuid_eax(0x80000008) & 0xff; + + if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36)) + return 36; + + return 32; +} + /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */ static void setup_pci_ram_top(void) { diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c index d8a3d60ae72..39aa0f63c65 100644 --- a/arch/x86/cpu/intel_common/cpu.c +++ b/arch/x86/cpu/intel_common/cpu.c @@ -127,6 +127,7 @@ int cpu_intel_get_info(struct cpu_info *info, int bclk) info->cpu_freq = ((msr.lo >> 8) & 0xff) * bclk * 1000000; info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU | 1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID; + info->address_width = cpu_phys_address_size(); return 0; } diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c index 1b4d3971b04..90a766c3c57 100644 --- a/arch/x86/cpu/x86_64/cpu.c +++ b/arch/x86/cpu/x86_64/cpu.c @@ -70,3 +70,8 @@ int x86_cpu_reinit_f(void) { return 0; } + +int cpu_phys_address_size(void) +{ + return CONFIG_CPU_ADDR_BITS; +} diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index 21a05dab7de..5b001bbee21 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -288,4 +288,13 @@ u32 cpu_get_family_model(void); */ u32 cpu_get_stepping(void); +/** + * cpu_phys_address_size() - Get the physical address size in bits + * + * This is 32 for older CPUs but newer ones may support 36. + * + * @return address size (typically 32 or 36) + */ +int cpu_phys_address_size(void); + #endif