From patchwork Fri Sep 4 15:34:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 1357661 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=Sj7u24br; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Bjhb35thZz9sTg for ; Sat, 5 Sep 2020 01:35:43 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 574CA822DB; Fri, 4 Sep 2020 17:35:23 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="Sj7u24br"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 646C1822DB; Fri, 4 Sep 2020 17:35:20 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C1A4F82294 for ; Fri, 4 Sep 2020 17:35:14 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=p.yadav@ti.com Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 084FZAtN066271; Fri, 4 Sep 2020 10:35:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1599233710; bh=kePXxcvCFxtEr7/BmxGnO64D5MyqtBItUxXDBp9IPLM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Sj7u24br7U79fU0jQ/pIWqoc1uGfY3LcXwJFeW3rS0EcU6Au4MLqgp1lau5FluB5R 9ivgOB3XHKPLB7EtBCtJqyLw9sjUlVAnkFbda5VhZBSucRBcV1BsbtO1JBOhp8G6se gFMfj757s7rHHR3scDwjDd9sNuAXHp6yenZLN8nE= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 084FZAwv046022 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 4 Sep 2020 10:35:10 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 4 Sep 2020 10:35:10 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 4 Sep 2020 10:35:10 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 084FZ10p025438; Fri, 4 Sep 2020 10:35:08 -0500 From: Pratyush Yadav To: Jagan Teki , Chris Packham , Vignesh R , CC: Pratyush Yadav , Sekhar Nori Subject: [PATCH v7 03/21] spi: cadence-qspi: Do not calibrate when device tree sets read delay Date: Fri, 4 Sep 2020 21:04:42 +0530 Message-ID: <20200904153500.3569-4-p.yadav@ti.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200904153500.3569-1-p.yadav@ti.com> References: <20200904153500.3569-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean If the device tree provides a read delay value, use that directly and do not perform the calibration procedure. This allows the device tree to over-ride the read delay value in cases where the read delay value obtained via calibration is incorrect. One such example is the Cypress Semper flash. It needs a read delay of 4 in octal DTR mode. But since the calibration procedure is run before the flash is switched in octal DTR mode, it yields a read delay of 2. A value of 4 works for both octal DTR and legacy modes. Signed-off-by: Pratyush Yadav --- drivers/spi/cadence_qspi.c | 26 +++++++++++++++++++++----- drivers/spi/cadence_qspi.h | 1 + 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 1e85749209..305f2ec0df 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -141,12 +141,20 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz) cadence_qspi_apb_controller_disable(priv->regbase); /* - * Calibration required for different current SCLK speed, requested - * SCLK speed or chip select + * If the device tree already provides a read delay value, use that + * instead of calibrating. */ - if (priv->previous_hz != hz || - priv->qspi_calibrated_hz != hz || - priv->qspi_calibrated_cs != spi_chip_select(bus)) { + if (plat->read_delay >= 0) { + cadence_spi_write_speed(bus, hz); + cadence_qspi_apb_readdata_capture(priv->regbase, 1, + plat->read_delay); + } else if (priv->previous_hz != hz || + priv->qspi_calibrated_hz != hz || + priv->qspi_calibrated_cs != spi_chip_select(bus)) { + /* + * Calibration required for different current SCLK speed, + * requested SCLK speed or chip select + */ err = spi_calibration(bus, hz); if (err) return err; @@ -320,6 +328,14 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) 255); plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20); plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20); + /* + * Read delay should be an unsigned value but we use a signed integer + * so that negative values can indicate that the device tree did not + * specify any signed values and we need to perform the calibration + * sequence to find it out. + */ + plat->read_delay = ofnode_read_s32_default(subnode, "cdns,read-delay", + -1); debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", __func__, plat->regbase, plat->ahbbase, plat->max_hz, diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index ae459c74a1..9dff2fdced 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -26,6 +26,7 @@ struct cadence_spi_platdata { u32 trigger_address; fdt_addr_t ahbsize; bool use_dac_mode; + int read_delay; /* Flash parameters */ u32 page_size;