@@ -10,6 +10,7 @@
#include "skeleton.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
+#include <dt-bindings/clock/qcom,ipq4019-gcc.h>
/ {
#address-cells = <1>;
@@ -61,7 +62,7 @@
blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
- clock = <&gcc 26>;
+ clock = <&gcc GCC_BLSP1_UART1_APPS_CLK>;
bit-rate = <0xFF>;
status = "disabled";
u-boot,dm-pre-reloc;
@@ -13,6 +13,8 @@
#include <dm.h>
#include <errno.h>
+#include <dt-bindings/clock/qcom,ipq4019-gcc.h>
+
struct msm_clk_priv {
phys_addr_t base;
};
@@ -20,7 +22,7 @@ struct msm_clk_priv {
ulong msm_set_rate(struct clk *clk, ulong rate)
{
switch (clk->id) {
- case 26: /*UART1*/
+ case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/
/* This clock is already initialized by SBL1 */
return 0;
break;
Its common to use dt-bindings instead of hard-coding clocks or resets. So lets use the imported Linux GCC bindings on IPQ40xx target. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> --- arch/arm/dts/qcom-ipq4019.dtsi | 3 ++- arch/arm/mach-ipq40xx/clock-ipq4019.c | 4 +++- 2 files changed, 5 insertions(+), 2 deletions(-)