diff mbox series

[v2,1/2] arm: socfpga: checks if FPGA is in user mode before enabling FPGA bridge

Message ID 20200818073330.157654-2-joyce.ooi@intel.com
State Deferred
Delegated to: Tom Rini
Headers show
Series arm: socfpga: enable CONFIG_BOOTCOMMAND for cyclone5 | expand

Commit Message

Joyce Ooi Aug. 18, 2020, 7:33 a.m. UTC 
From: Joyce Ooi <joyce.ooi@intel.com>

This patch adds a checking to ensure that FPGA is in user mode before
enabling FPGA bridge to prevent unexpected behavior or error.

Signed-off-by: Joyce Ooi <joyce.ooi@intel.com>
---
v2: this patch is added in patch version 2
---
 arch/arm/mach-socfpga/misc_gen5.c | 43 ++++++++++++++++++++++-----------------
 1 file changed, 24 insertions(+), 19 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 7209e8d6db7..7885ab2b6bc 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -221,26 +221,31 @@  void do_bridge_reset(int enable, unsigned int mask)
 	int i;
 
 	if (enable) {
-		socfpga_bridges_set_handoff_regs(!(mask & BIT(0)),
-						 !(mask & BIT(1)),
-						 !(mask & BIT(2)));
-		for (i = 0; i < 2; i++) {	/* Reload SW setting cache */
-			iswgrp_handoff[i] =
-				readl(socfpga_get_sysmgr_addr() +
-				      SYSMGR_ISWGRP_HANDOFF_OFFSET(i));
+		if (fpgamgr_test_fpga_ready()) {
+			socfpga_bridges_set_handoff_regs(!(mask & BIT(0)),
+							 !(mask & BIT(1)),
+							 !(mask & BIT(2)));
+			for (i = 0; i < 2; i++) {	/* Reload SW setting cache */
+				iswgrp_handoff[i] =
+					readl(socfpga_get_sysmgr_addr() +
+					      SYSMGR_ISWGRP_HANDOFF_OFFSET(i));
+			}
+
+			writel(iswgrp_handoff[2],
+			       socfpga_get_sysmgr_addr() +
+			       SYSMGR_GEN5_FPGAINFGRP_MODULE);
+			writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
+			writel(iswgrp_handoff[0],
+			       socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
+			writel(iswgrp_handoff[1], &nic301_regs->remap);
+
+			writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
+			writel(iswgrp_handoff[0],
+			       socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
+		} else {
+			puts("Bridges: Failed to enable because FPGA is not ");
+			puts("in user mode\n");
 		}
-
-		writel(iswgrp_handoff[2],
-		       socfpga_get_sysmgr_addr() +
-		       SYSMGR_GEN5_FPGAINFGRP_MODULE);
-		writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
-		writel(iswgrp_handoff[0],
-		       socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
-		writel(iswgrp_handoff[1], &nic301_regs->remap);
-
-		writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
-		writel(iswgrp_handoff[0],
-		       socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
 	} else {
 		writel(0, socfpga_get_sysmgr_addr() +
 		       SYSMGR_GEN5_FPGAINFGRP_MODULE);