From patchwork Mon Aug 10 08:17:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chuanjia Liu X-Patchwork-Id: 1342796 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256 header.s=dk header.b=TGEk/aRL; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BQCcg1wW8z9sPB for ; Mon, 10 Aug 2020 20:58:27 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E6D9B819EA; Mon, 10 Aug 2020 12:58:11 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.b="TGEk/aRL"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0BB02818F8; Mon, 10 Aug 2020 10:19:07 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MIME_BASE64_TEXT,RDNS_NONE,SPF_HELO_NONE, UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.2 Received: from mailgw01.mediatek.com (unknown [210.61.82.183]) by phobos.denx.de (Postfix) with ESMTP id 4D717819EA for ; Mon, 10 Aug 2020 10:19:01 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=chuanjia.liu@mediatek.com X-UUID: eff44b798dfd49c4a4ca9bc5abbb9975-20200810 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=v3E1z4lIkdECdwaQf/a57qDW1GEtvNljw9CoKHrRWJs=; b=TGEk/aRLyclzOs68hDUBvx2PMUrzyAas4rFJ3r8hNMHJSPdrtrDPliPtmHFbzRoRe1hx19UbfKL5rkp2XxFjdLtGqfRS1wzRRlPxpgWStrc8pMEJE6F6nP8yjd3Rgp4AlDS0FfrYuY2UOqbLDAidTw/Xr2xqaSg1esEO2EEWhzA=; X-UUID: eff44b798dfd49c4a4ca9bc5abbb9975-20200810 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 601226600; Mon, 10 Aug 2020 16:18:54 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 10 Aug 2020 16:18:51 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 10 Aug 2020 16:18:49 +0800 From: Chuanjia Liu To: Lukasz Majewski , Ryder Lee , CC: GSS_MTK_Uboot_upstream , Frank Wunderlich , , , Sam Shih , Henry Yen , , Chuanjia Liu Subject: [PATCH 1/5] clk: mediatek: add pciesys support for MT7622 SoC Date: Mon, 10 Aug 2020 16:17:08 +0800 Message-ID: <20200810081712.11242-2-Chuanjia.Liu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200810081712.11242-1-Chuanjia.Liu@mediatek.com> References: <20200810081712.11242-1-Chuanjia.Liu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Mailman-Approved-At: Mon, 10 Aug 2020 12:58:08 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean This patch adds pciesys support in clock driver for MediaTek MT7622 SoC. Signed-off-by: Henry Yen Signed-off-by: Chuanjia Liu --- drivers/clk/mediatek/clk-mt7622.c | 54 +++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index dc0ba71f10..bd86b5b974 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -453,6 +453,41 @@ static const struct mtk_gate peri_cgs[] = { GATE_PERI1(CLK_PERI_IRTX_PD, CLK_TOP_IRTX_SEL, 2), }; +/* pciesys */ +static const struct mtk_gate_regs pcie_cg_regs = { + .set_ofs = 0x30, + .clr_ofs = 0x30, + .sta_ofs = 0x30, +}; + +#define GATE_PCIE(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &pcie_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate pcie_cgs[] = { + GATE_PCIE(CLK_PCIE_P1_AUX_EN, CLK_TOP_P1_1MHZ, 12), + GATE_PCIE(CLK_PCIE_P1_OBFF_EN, CLK_TOP_4MHZ, 13), + GATE_PCIE(CLK_PCIE_P1_AHB_EN, CLK_TOP_AXI_SEL, 14), + GATE_PCIE(CLK_PCIE_P1_AXI_EN, CLK_TOP_HIF_SEL, 15), + GATE_PCIE(CLK_PCIE_P1_MAC_EN, CLK_TOP_PCIE1_MAC_EN, 16), + GATE_PCIE(CLK_PCIE_P1_PIPE_EN, CLK_TOP_PCIE1_PIPE_EN, 17), + GATE_PCIE(CLK_PCIE_P0_AUX_EN, CLK_TOP_P0_1MHZ, 18), + GATE_PCIE(CLK_PCIE_P0_OBFF_EN, CLK_TOP_4MHZ, 19), + GATE_PCIE(CLK_PCIE_P0_AHB_EN, CLK_TOP_AXI_SEL, 20), + GATE_PCIE(CLK_PCIE_P0_AXI_EN, CLK_TOP_HIF_SEL, 21), + GATE_PCIE(CLK_PCIE_P0_MAC_EN, CLK_TOP_PCIE0_MAC_EN, 22), + GATE_PCIE(CLK_PCIE_P0_PIPE_EN, CLK_TOP_PCIE0_PIPE_EN, 23), + GATE_PCIE(CLK_SATA_AHB_EN, CLK_TOP_AXI_SEL, 26), + GATE_PCIE(CLK_SATA_AXI_EN, CLK_TOP_HIF_SEL, 27), + GATE_PCIE(CLK_SATA_ASIC_EN, CLK_TOP_SATA_ASIC, 28), + GATE_PCIE(CLK_SATA_RBC_EN, CLK_TOP_SATA_RBC, 29), + GATE_PCIE(CLK_SATA_PM_EN, CLK_TOP_UNIVPLL2_D4, 30), +}; + /* ethsys */ static const struct mtk_gate_regs eth_cg_regs = { .sta_ofs = 0x30, @@ -554,6 +589,11 @@ static int mt7622_pericfg_probe(struct udevice *dev) return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, peri_cgs); } +static int mt7622_pciesys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs); +} + static int mt7622_ethsys_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs); @@ -597,6 +637,11 @@ static const struct udevice_id mt7622_pericfg_compat[] = { { } }; +static const struct udevice_id mt7622_pciesys_compat[] = { + { .compatible = "mediatek,mt7622-pciesys", }, + { } +}; + static const struct udevice_id mt7622_ethsys_compat[] = { { .compatible = "mediatek,mt7622-ethsys", }, { } @@ -660,6 +705,15 @@ U_BOOT_DRIVER(mtk_clk_pericfg) = { .flags = DM_FLAG_PRE_RELOC, }; +U_BOOT_DRIVER(mtk_clk_pciesys) = { + .name = "mt7622-clock-pciesys", + .id = UCLASS_CLK, + .of_match = mt7622_pciesys_compat, + .probe = mt7622_pciesys_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, +}; + U_BOOT_DRIVER(mtk_clk_ethsys) = { .name = "mt7622-clock-ethsys", .id = UCLASS_CLK,