diff mbox series

[v2] arm: socfpga: soc64: Document down boot_scratch_cold register usage

Message ID 20200810025556.30975-1-elly.siew.chin.lim@intel.com
State Accepted
Commit e2afbee50c5042fdbca78e2a6f86d9442af68783
Delegated to: Simon Goldschmidt
Headers show
Series [v2] arm: socfpga: soc64: Document down boot_scratch_cold register usage | expand

Commit Message

Siew Chin Lim Aug. 10, 2020, 2:55 a.m. UTC 
From: Chin Liang See <chin.liang.see@intel.com>

Document down the usage of boot_scratch_cold register to avoid
overlapping of usage in the code for S10 & Agilex.
The boot_scratch_cold register is generally used for passing
critical system info between SPL, U-Boot and Linux.

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>

---
v2: Mark boot_scratch_cold3 as reserved for customer use.
---
 arch/arm/mach-socfpga/include/mach/system_manager_soc64.h | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Ley Foon Tan Aug. 10, 2020, 6:51 a.m. UTC | #1 
> -----Original Message-----
> From: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> Sent: Monday, August 10, 2020 10:56 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Tan, Ley Foon
> <ley.foon.tan@intel.com>; See, Chin Liang <chin.liang.see@intel.com>;
> Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Ang, Chee Hong
> <chee.hong.ang@intel.com>; Chee, Tien Fong <tien.fong.chee@intel.com>;
> Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> Subject: [PATCH v2] arm: socfpga: soc64: Document down
> boot_scratch_cold register usage
> 
> From: Chin Liang See <chin.liang.see@intel.com>
> 
> Document down the usage of boot_scratch_cold register to avoid
> overlapping of usage in the code for S10 & Agilex.
> The boot_scratch_cold register is generally used for passing critical system
> info between SPL, U-Boot and Linux.
> 
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
> 
> ---
> v2: Mark boot_scratch_cold3 as reserved for customer use.
> ---
>  arch/arm/mach-socfpga/include/mach/system_manager_soc64.h | 8
> ++++++++
>  1 file changed, 8 insertions(+)

Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>

Regards
Ley Foon
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index c90f63a754..e5bb81a7a2 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -46,13 +46,21 @@  void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
 #define SYSMGR_SOC64_GPO			0xe4
 #define SYSMGR_SOC64_GPI			0xe8
 #define SYSMGR_SOC64_MPU			0xf0
+/* store qspi ref clock */
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD0		0x200
+/* store osc1 clock freq */
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD1		0x204
+/* store fpga clock freq */
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD2		0x208
+/* reserved for customer use */
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD3		0x20c
+/* store PSCI_CPU_ON value */
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD4		0x210
+/* store PSCI_CPU_ON value */
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD5		0x214
+/* store VBAR_EL3 value */
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD6		0x218
+/* store VBAR_EL3 value */
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD7		0x21c
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD8		0x220
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD9		0x224