diff mbox series

[v2] arm: socfpga: soc64: Check FPGA Config status register before bridge reset

Message ID 20200806035629.18824-1-chee.hong.ang@intel.com
State Accepted
Commit 6b6307ed22121a38c5b1a5198e737e78b7135312
Delegated to: Simon Goldschmidt
Headers show
Series [v2] arm: socfpga: soc64: Check FPGA Config status register before bridge reset | expand

Commit Message

Ang, Chee Hong Aug. 6, 2020, 3:56 a.m. UTC
Instead of querying SDM for FPGA configuration status through mailbox
messages, U-Boot now checks System Manager's FPGA Config status register
for FPGA configuration status before resetting bridge.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
 arch/arm/mach-socfpga/include/mach/misc.h              |  5 +++++
 .../mach-socfpga/include/mach/system_manager_soc64.h   |  6 +++++-
 arch/arm/mach-socfpga/misc_s10.c                       | 18 ++++++++++--------
 3 files changed, 20 insertions(+), 9 deletions(-)

Comments

Tan, Ley Foon Aug. 6, 2020, 6 a.m. UTC | #1
> -----Original Message-----
> From: Ang, Chee Hong <chee.hong.ang@intel.com>
> Sent: Thursday, August 6, 2020 11:56 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Tom Rini <trini@konsulko.com>; See,
> Chin Liang <chin.liang.see@intel.com>; Tan, Ley Foon
> <ley.foon.tan@intel.com>; Ang, Chee Hong <chee.hong.ang@intel.com>;
> Chee, Tien Fong <tien.fong.chee@intel.com>; Lim, Elly Siew Chin
> <elly.siew.chin.lim@intel.com>
> Subject: [PATCH v2] arm: socfpga: soc64: Check FPGA Config status register
> before bridge reset
> 
> Instead of querying SDM for FPGA configuration status through mailbox
> messages, U-Boot now checks System Manager's FPGA Config status register
> for FPGA configuration status before resetting bridge.
> 
> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
> ---
>  arch/arm/mach-socfpga/include/mach/misc.h              |  5 +++++
>  .../mach-socfpga/include/mach/system_manager_soc64.h   |  6 +++++-
>  arch/arm/mach-socfpga/misc_s10.c                       | 18 ++++++++++--------
>  3 files changed, 20 insertions(+), 9 deletions(-)
> 

Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>

Regards
Ley Foon
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index a85c5ae..649d2f6 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -39,6 +39,11 @@  void socfpga_init_security_policies(void);
 void socfpga_sdram_remap_zero(void);
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+	defined(CONFIG_TARGET_SOCFPGA_AGILEX)
+int is_fpga_config_ready(void);
+#endif
+
 void do_bridge_reset(int enable, unsigned int mask);
 void socfpga_pl310_clear(void);
 void socfpga_get_managers_addr(void);
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index c90f63a..5e3f54a 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -88,8 +88,12 @@  void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
 #define SYSMGR_ECC_OCRAM_EN	BIT(0)
 #define SYSMGR_ECC_OCRAM_SERR	BIT(3)
 #define SYSMGR_ECC_OCRAM_DERR	BIT(4)
-#define SYSMGR_FPGAINTF_USEFPGA	0x1
+#define SYSMGR_FPGACONFIG_FPGA_COMPLETE		BIT(0)
+#define SYSMGR_FPGACONFIG_EARLY_USERMODE	BIT(1)
+#define SYSMGR_FPGACONFIG_READY_MASK	(SYSMGR_FPGACONFIG_FPGA_COMPLETE | \
+					 SYSMGR_FPGACONFIG_EARLY_USERMODE)
 
+#define SYSMGR_FPGAINTF_USEFPGA	0x1
 #define SYSMGR_FPGAINTF_NAND	BIT(4)
 #define SYSMGR_FPGAINTF_SDMMC	BIT(8)
 #define SYSMGR_FPGAINTF_SPIM0	BIT(16)
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index 670bfa1..52868fb 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -151,17 +151,19 @@  int arch_early_init_r(void)
 	return 0;
 }
 
+/* Return 1 if FPGA is ready otherwise return 0 */
+int is_fpga_config_ready(void)
+{
+	return (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGA_CONFIG) &
+		SYSMGR_FPGACONFIG_READY_MASK) == SYSMGR_FPGACONFIG_READY_MASK;
+}
+
 void do_bridge_reset(int enable, unsigned int mask)
 {
 	/* Check FPGA status before bridge enable */
-	if (enable) {
-		int ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
-
-		if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
-			ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS);
-
-		if (ret)
-			return;
+	if (!is_fpga_config_ready()) {
+		puts("FPGA not ready. Bridge reset aborted!\n");
+		return;
 	}
 
 	socfpga_bridges_reset(enable);